VLIW-Architecture

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VLIW-Architecture

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Simulation of a 32-bit 5-stage pipelined VLIW processor with an assembly file as input and track the processor register file's updating it constantly.

VLIW-Architecture 최신버젼 다운로드

최종 버전 다운로드 (.zip)

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# VLIW-Architecture
A Python - Verilog combination that simulates the working of a 32-bit 5-stage VLIW processor from input assembly code while monitoring the updates in the processor register file.

The VLIW processor contains the following modules:
- Two 32-bit pipelined recursive doubling adders
- One 32-bit pipelined wallace multiplier
- Two 32-bit pipelined floating point adders (IEEE 32-bit floating point representation)
- One 32-bit pipelined floating point multiplier (IEEE 32-bit floating point representation)
- One logic unit
- One memory load unit
- One memory store unit
- One register move unit

Instruction format is given in instructions.txt.

## Demo
- Demo of execution of Test_Cases\demo_1.ss
![Demo of execution of Test_Cases\demo_1.ss](https://github.com/thegamingbot/VLIW-Architecture/blob/main/Demo/demo_1.gif)
- Demo of execution of Test_Cases\demo_2.ss
![Demo of execution of Test_Cases\demo_2.ss](https://github.com/thegamingbot/VLIW-Architecture/blob/main/Demo/demo_2.gif)
- Demo of execution of Test_Cases\demo_3.ss
![Demo of execution of Test_Cases\demo_3.ss](https://github.com/thegamingbot/VLIW-Architecture/blob/main/Demo/demo_3.gif)

## Usage
- For UNIX users
  - ```./setup.sh```
- For Windows users
  - Install Icarus Verilog 
- ```python3 main.py```

## Technologies used
- Python3
- Verilog

VLIW-Architecture

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