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aegis

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Open source FPGA silicon

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- - ci-deb.yml
  - ci-docker.yml
  - ci.yml
- - Cargo.toml
  - descriptor.schema.json
- - Cargo.toml
- - Cargo.toml
- - bram.md
  - clb.md
  - clock.md
  - configuration.md
  - dsp.md
  - io.md
  - pdk.md
  - README.md
  - routing.md
  - serdes.md
- - blinky.pcf
  - blinky.v
  - default.nix
- - aegis_genip.dart
  - aegis_sim.dart
- - descriptor.schema.json
- - aegis_ip.dart
- - descriptor_test.dart
- .envrc
- .gitignore
- analysis_options.yaml
- CHANGELOG.md
- pubspec.lock
- pubspec.lock.json
- pubspec.yaml
- README.md
- aegis.cc
- aegis_test.cc
- - deb.nix
  - default.nix
- - default.nix
- - default.nix
- - default.nix
- - default.nix
- - default.nix
- - default.nix
- - default.nix
- - default.nix
- - blinky.pcf
  - blinky_test.v
  - default.nix
- - counter.pcf
  - counter.v
  - default.nix
- - clb_props.sv
  - default.nix
  - lut4_props.sv
  - tile_props.sv
- - default.nix
- - default.nix
  - gates.pcf
  - gates.v
- - default.nix
  - shift.pcf
  - shift.v
- - cells_sim.v
  - comb.v
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  - default.nix
- - default.nix
.gitignore
Cargo.lock
Cargo.toml
devices.nix
flake.lock
flake.nix
LICENSE
README.md

// repository documentation

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# Aegis

Aegis is a fully open-source FPGA, from the silicon up.

Open-source FPGA efforts have made huge strides: projects like Project
IceStorm and Apicula reverse-engineer proprietary bitstream formats,
OpenFPGA and FABulous generate open FPGA fabric from architecture
descriptions, and Cologne Chip's GateMate ships a commercial FPGA with a
fully open-source toolchain. Where these projects each tackle a piece of
the puzzle, Aegis is a full-stack, end-to-end open-source FPGA: fabric
generation, synthesis, place-and-route, bitstream packing, simulation,
and tapeout all live in one project, designed from the ground up for open
source. From HDL to GDS, nothing is behind a proprietary wall.

The project generates parameterized FPGA devices with LUT4, BRAM, DSP,
SerDes, and clock management tiles, along with everything needed to
synthesize user designs onto them and tape out the fabric itself to a
foundry via open PDKs and shuttle services like
[wafer.space](https://wafer.space).

## Devices

### Aegis Luna 1

A compact Aegis device targeting GF180MCU via [wafer.space](https://wafer.space)

| Resource          | Count                     |
|-------------------|---------------------------|
| Fabric            | 23 x 23 tiles (529 total) |
| LUT4 (CLB)        | 437                       |
| BRAM (128x8)      | 46 tiles                  |
| DSP18 (18x18 MAC) | 46 tiles                  |
| I/O tiles         | 92 (25 bonded bidir)      |
| SerDes            | 0                         |
| Clock tiles       | 1 (4 outputs)             |
| Routing tracks    | 1 per edge                |

```bash
nix build .#luna-1          # Generate IP (SV, JSON, chipdb, techmap)
nix build .#luna-1-tapeout  # Full RTL-to-GDS for fab submission
```

### Aegis Terra 1

A larger Aegis device targeting Sky130.

| Resource          | Count         |
|-------------------|---------------|
| LUT4              | ~2880         |
| BRAM (128x8)      | 128 tiles     |
| DSP18 (18x18 MAC) | 64 tiles      |
| I/O pads          | 224           |
| SerDes            | 4             |
| Clock tiles       | 2 (8 outputs) |
| Routing tracks    | 4 per edge    |

```bash
nix build .#terra-1          # Generate IP (SV, JSON, chipdb, techmap)
nix build .#terra-1-tapeout  # Full RTL-to-GDS for fab submission
```

## Toolchain

Each device gets a complete FPGA toolchain via the `tools` output:

```bash
# Synthesize a Verilog design to Aegis cells
yosys -c synth.tcl  # using $tools/share/yosys/aegis/*_cells.v + *_techmap.v

# Place and route on the fabric
nextpnr-aegis-terra_1 --json design_mapped.json --write design_pnr.json

# Pack into a bitstream
terra_1-pack --pnr design_pnr.json --output design.bin

# Simulate with the bitstream loaded
terra_1-sim --bitstream design.bin --cycles 1000 --vcd waves.vcd
```

## ASIC Tapeout

The tapeout pipeline synthesizes the FPGA fabric itself to PDK standard cells:

```bash
nix build .#terra-1-tapeout
ls result/
# terra_1_synth.v      - gate-level netlist (Yosys)
# terra_1_final.def    - placed & routed layout (OpenROAD)
# terra_1.gds          - GDS2 for fab submission
# terra_1_layout.png   - layout render
# timing.rpt           - timing analysis
# power.rpt            - power report
```

Supports GF180MCU (wafer.space) and Sky130 PDKs.

## Installation

### Nix (recommended)

Requires [Nix](https://nixos.org/) with flakes enabled.

```bash
# Build the default package (aegis-ip-tools)
nix build

# Build Terra 1 IP
nix build .#terra-1

# Run the blinky example as a check
nix build .#checks.$(nix eval --raw nixpkgs#system).terra-1-blinky

# Enter development shell
nix develop
```

### Docker

Pre-built multi-arch images are available from GitHub Container Registry:

```bash
docker pull ghcr.io/midstall/aegis-terra_1:latest

# Run with your design directory mounted
docker run -v $(pwd):/workspace -it ghcr.io/midstall/aegis-terra_1:latest
```

Images are tagged by git SHA and release version (e.g. `:v1.0.0`).

To build locally with Nix:

```bash
nix build .#terra-1-docker
docker load < result
```

### Debian/Ubuntu

Download `.deb` packages from [GitHub Releases](https://github.com/MidstallSoftware/aegis/releases) (amd64 and arm64):

```bash
sudo dpkg -i aegis-terra-1_*.deb
```

This installs `aegis-pack`, `aegis-sim`, `nextpnr-generic`, device-specific
wrappers (`terra_1-sim`, `terra_1-pack`, `nextpnr-aegis-terra_1`), and support
files under `/usr/share/aegis/`.

To build locally with Nix:

```bash
nix build .#terra-1-deb
```

## Architecture

The FPGA fabric is generated by ROHD (a Dart HDL framework) and outputs
synthesizable SystemVerilog. The architecture follows Xilinx-style conventions:

- **CLB**: LUT4 + D flip-flop + MUXCY carry chain (18-bit config)
- **Tile**: CLB + 4-directional routing muxes (46-bit config)
- **BRAM**: Dual-port 128x8 block RAM (8-bit config)
- **DSP**: 18x18 multiply-accumulate with optional pipeline (16-bit config)
- **IO**: Bidirectional pad with input/output registers (8-bit config)
- **SerDes**: Protocol-agnostic serializer/deserializer (32-bit config)
- **Clock**: 4-output clock divider with phase control (49-bit config)

Configuration is loaded via a serial shift register chain:
clock tiles -> IO tiles -> SerDes tiles -> fabric tiles (row-major).

## Community

- **Discord**: [Join the server](https://discord.gg/HRhetTVcHG)
- **Contact**: [inquire@midstall.com](mailto:inquire@midstall.com)

## Related Projects

- **[OpenFPGA](https://github.com/lnis-uofu/OpenFPGA)** - An open-source FPGA
  IP generator from the University of Utah. Given an XML architecture
  description, it generates synthesizable Verilog for a complete FPGA fabric
  along with bitstream tooling and self-testing infrastructure. Silicon-proven
  through DARPA's POSH program.

- **[FABulous](https://github.com/FPGA-Research-Manchester/FABulous)** - An
  open-source embedded FPGA (eFPGA) framework from the University of Manchester.
  Generates custom FPGA fabric from CSV-based configuration and integrates Yosys
  and nextpnr. Silicon-proven with 12+ tapeouts across nodes from TSMC 180nm
  down to 28nm CMOS.

- **[Cologne Chip GateMate](https://colognechip.com/programmable-logic/gatemate/)**
  - A commercial FPGA on GlobalFoundries 28nm with a fully open-source,
  license-free toolchain built on Yosys, nextpnr, and openFPGALoader. The
  silicon itself is proprietary, but it is notable as one of the few commercial
  FPGAs to embrace open-source EDA tools end-to-end.