Processor-UVM-Verification
System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
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최종 버전 다운로드 (.zip)- Adder.v
- adder_internal.v
- ALU.v
- black_box.v
- comp.v
- Control_Unit.v
- data_mem.v
- full_adder.v
- grey_box.v
- halfadder.v
- inst_mem.v
- instructions (Init_Reg).txt
- instructions - Copy.txt
- instructions.txt
- instructions_t1.txt
- instructions_t2.txt
- instructions_t3.txt
- Main_Processor (copy).v
- Main_Processor (final Working Copy).v
- Main_Processor.v
- mux2_1_1bit.v
- mux4_1_16bit.v
- reg_file.v
- stg_final.v
- wallace_8bit.v
- Makefile.vcs
- processor_agent.sv
- processor_driver.sv
- processor_env.sv
- processor_interface.sv
- processor_monitor.sv
- processor_scoreboard.sv
- processor_sequence.sv
- processor_subscriber.sv
- processor_test.sv
- processor_testbench_pkg.sv
- top.sv
- Report.pdf
- README.md
// repository documentation
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