Report-for-Breadboard-CPU-Project

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Report-for-Breadboard-CPU-Project

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# 8-Bit CPU Implementation (Breadboard + Arduino)

## Project Overview

This project implements a working **8-bit Central Processing Unit (CPU)** using **TTL logic chips and Arduino boards**. The goal of the project is to demonstrate how a basic CPU operates at the hardware level, including instruction fetch, decode, and execution.

The CPU is implemented on a **breadboard using TTL components** to mimic the behavior of registers, buses, and arithmetic logic units. Arduino boards are used to implement the **control unit and memory unit**, allowing the hardware components to operate together as a complete processor.

The CPU executes a small **Instruction Set Architecture (ISA)** consisting of **12 instructions** and operates using an **8-bit wide data bus**.

---

# Hardware Implementation

## Registers Implementation

The CPU registers are implemented using **TTL counter chips (74LS469)**.

Although these chips are counters, they are used as **general-purpose registers** by:

- Freezing the counter operation.
- Loading required data using the **parallel load pins** when needed.

This allows the chips to function as **8-bit storage registers**.

The registers implemented in the CPU include:

- **Program Counter (PC)**
- **Memory Address Register (MAR)**
- **Instruction Register (IR)**
- **Accumulator Register (A)**
- **Buffer Register (B)**
- **Output Register (OUT)**

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## Bus Implementation

The CPU uses a **common 8-bit data bus** for communication between all components.

The bus is implemented directly on the **breadboard** using the **horizontal rows of the breadboard**.

All registers, memory units, and the ALU connect to these lines through **bus transceivers**.

This forms a shared communication medium allowing components to exchange data.

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## Bus Control

Data flow onto and off the bus is controlled using **74LS245 Octal Bus Transceiver chips**.

These chips:

- Allow registers to **place data onto the bus**
- Allow registers to **read data from the bus**
- Prevent bus contention by ensuring **only one component drives the bus at a time**

The direction and enabling of these transceivers are controlled using **control signals generated by the control unit**.

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## Output Display

The **OUT register** stores the final result of computations.

The contents of this register are connected to a **seven-segment display**, allowing the output of the CPU to be visually displayed.

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# Memory System

The memory unit of the CPU is implemented using **an Arduino board**.

Two separate memories are maintained using arrays inside the Arduino.

---

## Instruction Memory

Instruction memory stores the program to be executed.

- **Size:** 256 locations  
- **Width:** 8 bits per instruction

This memory is implemented using an **array inside the Arduino program**.

Although the original report mentions \(2^4\) instruction locations, the actual implementation uses **256 instruction locations**.

---

## Data Memory

Data memory stores operands used during program execution.

- **Size:** 16 locations  
- **Width:** 8 bits

[ OPCODE | OPERAND ]
4 bits 4 bits

The **4-bit operand field** is used as the **memory address** during load and store operations.

Since 4 bits can represent:
2^4 = 16 addresses

the data memory size is limited to **16 locations**.

---

## Memory Unit Behavior

The Arduino memory unit dynamically changes the behavior of its pins depending on the operation.

- When the CPU **sends an address**, the Arduino pins act as **inputs**.
- When the CPU **requests data or instructions**, the pins act as **outputs**.

All this behavior is handled internally by the **pre-written Arduino memory code**, allowing the memory unit to interact correctly with the CPU bus.

---

# Control Unit

The control unit is implemented using **three Arduino boards**.

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## Master Control Arduino

The master Arduino is responsible for:

- Generating the **clock signal** for the entire CPU
- Generating the  **clock signal** for the program counter.
- Receiving instructions from the **Instruction Register**
- **Decoding the opcode**
- Sending commands to the slave control units

This Arduino essentially acts as the **main controller of the CPU control logic**.

---

## Slave Control Arduinos

The CPU requires **20 control signals** to coordinate the operation of registers, memory, and the ALU.

To generate all control signals, **two slave Arduino boards** are used.

- Each slave Arduino outputs **10 control signals**
- The master Arduino communicates with the slaves using **I²C communication**
- Based on the decoded instruction, the master sends commands to the slaves to activate the required control signals

---

# Control Signals

The CPU uses **20 control signals** to coordinate all operations.

Examples include:

- MAR Read
- MAR Write
- IR Read
- IR Write
- A Read
- A Write
- Buffer Read
- PC Write
- OUT Enable
- Memory Read/Write
- Control Unit Read/Write
- ALU operation selection signals

These signals determine **which component reads from or writes to the bus during each clock cycle**.

---

# Instruction Set Architecture (ISA)

The CPU supports **12 instructions**, each represented by a **4-bit opcode**.

| Instruction | Opcode |
|-------------|--------|
| LDA | 0000 |
| ADD | 0001 |
| SUB | 0010 |
| STA | 0011 |
| LDI | 0100 |
| JMP | 0101 |
| JC | 0110 |
| JZ | 0111 |
| OUT | 1000 |
| HLT | 1001 |
| AND | 1010 |
| OR | 1011 |

Each instruction occupies **1 byte**.

---

# CPU Components

### Program Counter (PC)

Stores the address of the next instruction to be executed.

---

### Memory Address Register (MAR)

Holds the address of the memory location that needs to be accessed.

---

### Instruction Register (IR)

Stores the instruction currently being executed.

---

### Accumulator (A Register)

Stores results of ALU operations and intermediate values.

---

### Buffer Register (B Register)

Stores the second operand for ALU operations.

---

### Arithmetic Logic Unit (ALU)

Performs arithmetic and logical operations including:

- Addition
- Subtraction
- AND
- OR

---

### Output Register (OUT)

Stores the final result that is sent to the seven-segment display.

---

### Flag Registers

Two flags are used:

- **Carry Flag** — Set when an arithmetic operation produces a carry.
- **Zero Flag** — Set when the result of an operation is zero.

---

# Instruction Execution Stages

Every instruction begins with **four common fetch cycles**.

---

## Common Fetch Cycles

### Cycle 1

The **Program Counter (PC)** sends the instruction address to the **Memory Address Register (MAR)**.

---

### Cycle 2

Memory is accessed using the address stored in MAR.

---

### Cycle 3

The instruction from memory is placed on the bus and loaded into the **Instruction Register (IR)**.

---

### Cycle 4

The instruction is written into the IR and the **control unit decodes the opcode**.

---

# Instruction Execution Cycles

## LDA (Load Accumulator)

Cycle 5  
Address field from the instruction is loaded into MAR.

Cycle 6  
Memory location is accessed.

Cycle 7  
Data from memory is loaded into the accumulator.

---

## LDI (Load Immediate)

Cycle 5  
Immediate value from the instruction is placed on the bus and loaded into the accumulator.

---

## STA (Store Accumulator)

Cycle 5  
Address is loaded into MAR.

Cycle 6  
Memory location is accessed.

Cycle 7  
Accumulator value is written into memory.

---

## ADD

Cycle 5  
Address is loaded into MAR.

Cycle 6  
Memory operand is accessed.

Cycle 7  
Operand is loaded into the buffer register.

Cycle 8  
ALU performs addition and the result is stored in the accumulator.

---

## SUB, AND, OR

These instructions follow the **same execution sequence as ADD**, with the ALU configured to perform the required operation.

---

## OUT

Cycle 5  
The contents of the accumulator are transferred to the **OUT register** for display.

---

# Jump Instructions

## JMP (Unconditional Jump)

Cycle 5  
The address field of the instruction is loaded into MAR.

Cycle 6  
The system is configured such that the **Program Counter begins counting from the value stored in the MAR register**.

The MAR output is always connected to the PC and when the jump occurs the value from MAR is loaded into the PC through the appropriate control signals.

---

## JC (Jump if Carry)

This instruction performs a jump **only if the Carry flag is set**.

---

## JZ (Jump if Zero)

This instruction performs a jump **only if the Zero flag is set**.

---

# Clock Operation

The **master Arduino** generates the clock signal for the entire CPU.

Each instruction may take **up to 8 clock cycles** depending on the instruction.

If an instruction completes earlier, the remaining control signals remain inactive until the next instruction begins.

Seperate clock which is 8 times slower than the clock fed to all the registers is fed to the program counter so that it write new address onto bus after all the eight cycles complete.

---

# Summary

This project demonstrates the implementation of a working **8-bit CPU** using:

- TTL logic chips for registers and ALU
- Breadboard bus architecture - 
  **8 horizontal lines** of the breadboard are used.
  Each line represents **one bit of the data bus**.
- Arduino boards for control and memory

The design illustrates the fundamental operations of a processor including:

- Instruction fetch
- Instruction decode
- Instruction execution
- Data movement through control signals

Report-for-Breadboard-CPU-Project

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