qick
QICK: Quantum Instrumentation Control Kit
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최종 버전 다운로드 (.zip)- test_zcu111.yml
- update_version.yml
- wheels.yml
- dependabot.yml
- SUPPORT.md
- aws_demo.ipynb
- config.template
- qick.service
- qick_client.py
- README.md
- start_qick_client.sh
- user_client.py
- custom.css
- QICKpapers_count_Jan26.png
- QICKpapers_count_May26.png
- QICKpapers_qubit_types_Jan26.png
- QICKpapers_qubit_types_May26.png
- QICKpapers_qubit_types_pie_May26.png
- QICKpapers_scaling_Jan26_final.png
- QICKpapers_scaling_May26.png
- QICKpapers_scaling_pie_May26.png
- boardpic_cartoon.PNG
- Bootmodeswitch.png
- ciscorouter.PNG
- correctpynqversion.PNG
- Eafterwrite.PNG
- jupyternotebook1.PNG
- jupyternotebook2.PNG
- largeimagefile.PNG
- port_forward.png
- pscpfolderstructure.PNG
- pullingdataofftheboard.PNG
- pushingdatatotheboard.PNG
- putty1.PNG
- putty2.PNG
- putty3.PNG
- pynqstartup.PNG
- pynqversion.PNG
- static_ip.png
- writetoEdrive.PNG
- asmv1_cheatsheet.rst
- changing_fs.rst
- freq_matching.rst
- gen_config.rst
- index.rst
- playing_pulses.rst
- reference_clock.rst
- timing.rst
- units.rst
- conf.py
- contact.rst
- firmware.rst
- index.rst
- make.bat
- Makefile
- modules.rst
- papers.rst
- quick_start.rst
- README.md
- requirements.txt
- board.xml
- LICENSE
- part0_pins.xml
- preset.xml
- rfsoc4x2_board.png
- xitem.json
- logoQICK_128x128.png
- bram_dp_xpm.sv
- fifo_dc_axi_xpm.sv
- fifo_xpm.sv
- lo_spi_mux.vhd
- lo_spi_mux_v2.vhd
- vect2bits_16.v
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- data_iq.txt
- tb.sv
- tb_avg.sv
- tb_avg_buffer.sv
- tb_avg_top.sv
- tb_buffer.sv
- tb_buffer_top.sv
- tb_waves.wcfg
- avg.sv
- avg_buffer.v
- avg_top.v
- axi_slv_avg_buf.vhd
- axis_avg_buffer.v
- buffer.sv
- buffer_top.v
- data_reader.vhd
- outreg.sv
- synchronizer_n.vhd
- axis_avg_buffer_v1_0.tcl
- axis_avg_buffer_v1_1.tcl
- axis_avg_buffer_v1_2.tcl
- component.xml
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- axi_mst_0.xci
- axi_slv_0.xci
- tb.sv
- tb_axi_mst.sv
- tb_axis_buffer_ddr_behav.wcfg
- axi_mst.sv
- axi_mst_read.sv
- axi_mst_write.sv
- axi_slv.v
- axis_buffer_ddr.sv
- synchronizer_n.vhd
- axis_buffer_ddr_v1_1.tcl
- axis_buffer_ddr_v1_v1_0.tcl
- component.xml
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- axis_cdcsync_ooc.xdc
- axis_cdcsync_v1.sv
- cdcsync.sv
- axis_cdcsync_v1_v1_0.tcl
- component.xml
- axis_constant.vhd
- axis_constant_v1_0.tcl
- component.xml
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- axi_slv.vhd
- axis_constant_iq.vhd
- synchronizer_n.vhd
- tb.sv
- axis_constant_iq_v1_0.tcl
- component.xml
- dds_compiler_0.veo
- dds_compiler_0.vho
- dds_compiler_0.xci
- dds_compiler_0.xml
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- fir_compiler_0.veo
- fir_compiler_0.vho
- fir_compiler_0.xci
- fir_compiler_0.xml
- tb.sv
- axis_dyn_readout_v1.v
- ctrl_dyn_ro_v1.sv
- down_conversion.v
- down_conversion_fir.v
- fir.coe
- fir_compiler_0.v
- readout_top.v
- axis_dyn_readout_v1_v1_0.tcl
- component.xml
- axi_mst_0.xci
- dds_0.xci
- tb_dds_top.sv
- tb_mod_ctrl.sv
- dds_ctrl.v
- dds_top.v
- mod_ctrl.sv
- tb_iir.sv
- iir.sv
- iir_iq.sv
- latency_reg.v
- synchronizer_n.vhd
- tb.sv
- tb_kidsim.sv
- tb_kidsim_top.sv
- tb_punct.sv
- tdm_demux.sv
- axi_slv.v
- axis_kidsim_v3.sv
- kidsim.sv
- kidsim_top.sv
- prod.sv
- punct.sv
- axis_kidsim_v3_v1_0.tcl
- component.xml
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- dds_0.veo
- dds_0.xci
- fir_0.coe
- fir_1.coe
- fir_2.coe
- fir_3.coe
- fir_4.coe
- fir_5.coe
- fir_6.coe
- fir_7.coe
- fir_0.xci
- fir_1.xci
- fir_2.xci
- fir_3.xci
- fir_4.xci
- fir_5.xci
- fir_6.xci
- fir_7.xci
- fir.tcl.template
- ipgen.tcl
- add.tcl
- fir.tcl
- fir_0.veo
- gen.pl
- Makefile
- base_h.fda
- base_h.mat
- gen_coeffs_multilane.m
- gen_input.m
- gen_input_multi.m
- read_dout.m
- read_dout_all.m
- conv_pkg.vhd
- single_reg_w_init.vhd
- srl17e.vhd
- srl33e.vhd
- ssr_8x8.vhd
- ssr_8x8_entity_declarations.vhd
- synth_reg.vhd
- synth_reg_reg.vhd
- synth_reg_w_init.vhd
- xlclockdriver_rd.vhd
- ssrfft_8x8.vhd
- tb.vhd
- tb.sv
- axi_slv.vhd
- axis_pfb_readout_v2.v
- ddsprod.sv
- ddsprod_v.sv
- firs.sv
- pfb.sv
- pfb_dds_mux.sv
- pfb_mux.sv
- pimod.vhd
- axis_pfb_readout_v2_v1_0.tcl
- component.xml
- README
- axi_mst_0.xci
- dds_0.xci
- cmult_16x16.v
- cmult_sub.v
- dds_ctrl.sv
- dds_top.sv
- mult_32x32.v
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- conv_pkg.vhd
- single_reg_w_init.vhd
- srl17e.vhd
- srl33e.vhd
- ssr_8x64.vhd
- ssr_8x64_entity_declarations.vhd
- synth_reg.vhd
- synth_reg_reg.vhd
- synth_reg_w_init.vhd
- xlclockdriver_rd.vhd
- framing.vhd
- README
- ssrfft_8x64_sync.vhd
- tb.vhd
- tlast_gen.vhd
- fir_0.coe
- fir_1.coe
- fir_2.coe
- fir_3.coe
- fir_4.coe
- fir_5.coe
- fir_6.coe
- fir_7.coe
- fir_0.xci
- fir_1.xci
- fir_2.xci
- fir_3.xci
- fir_4.xci
- fir_5.xci
- fir_6.xci
- fir_7.xci
- fir.tcl.template
- ipgen.tcl
- add.tcl
- fir.tcl
- fir_0.veo
- gen.pl
- Makefile
- firs.sv
- pfb.sv
- pfb_cfg.vhd
- pfb_chsel.sv
- pfb_ctrl.vhd
- pfb_ctrl_pkg.vhd
- pfb_framing.vhd
- pfb_reorder.sv
- pfb_swap.sv
- pfb_switch.v
- pfb_top.sv
- pimod_pfb.vhd
- zn_nb.vhd
- axis_pfb_readout_v3.xdc
- dds_ctrl.xdc
- dds_top.xdc
- ddsprod.xdc
- tb.sv
- tb_dds_ctrl.sv
- tb_dds_top.sv
- tb_ddsprod.sv
- tb_pfb.sv
- tb_pfb_chsel.sv
- tb_pfb_top.sv
- tdm_demux.sv
- axi_slv.vhd
- axis_pfb_readout_v3.v
- ddsprod.sv
- ddsprod_v.sv
- latency_reg.v
- pfb_readout.v
- axis_pfb_readout_v3_v1_0.tcl
- component.xml
- README
- dds_0.xci
- cmult_16x16.v
- cmult_sub.v
- dds_ctrl.sv
- dds_top.sv
- mult_32x32.v
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- conv_pkg.vhd
- single_reg_w_init.vhd
- srl17e.vhd
- srl33e.vhd
- ssr_8x64.vhd
- ssr_8x64_entity_declarations.vhd
- synth_reg.vhd
- synth_reg_reg.vhd
- synth_reg_w_init.vhd
- xlclockdriver_rd.vhd
- framing.vhd
- README
- ssrfft_8x64_sync.vhd
- tb.vhd
- tlast_gen.vhd
- fir_0.coe
- fir_1.coe
- fir_2.coe
- fir_3.coe
- fir_4.coe
- fir_5.coe
- fir_6.coe
- fir_7.coe
- fir_0.xci
- fir_1.xci
- fir_2.xci
- fir_3.xci
- fir_4.xci
- fir_5.xci
- fir_6.xci
- fir_7.xci
- fir.tcl.template
- ipgen.tcl
- add.tcl
- fir.tcl
- fir_0.veo
- gen.pl
- Makefile
- firs.sv
- pfb.sv
- pfb_cfg.vhd
- pfb_chsel.sv
- pfb_ctrl.vhd
- pfb_ctrl_pkg.vhd
- pfb_framing.vhd
- pfb_reorder.sv
- pfb_swap.sv
- pfb_switch.v
- pfb_top.sv
- pimod_pfb.vhd
- zn_nb.vhd
- axis_pfb_readout_v3.xdc
- dds_ctrl.xdc
- dds_top.xdc
- ddsprod.xdc
- tb.sv
- axi_slv.v
- axis_pfb_readout_v4.v
- ddsprod.sv
- ddsprod_v.sv
- latency_reg.v
- pfb_readout.v
- axis_pfb_readout_v4_v1_0.tcl
- component.xml
- README
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- conv_pkg.vhd
- single_reg_w_init.vhd
- srl17e.vhd
- srl33e.vhd
- ssr_8x256.vhd
- ssr_8x256_entity_declarations.vhd
- synth_reg.vhd
- synth_reg_reg.vhd
- synth_reg_w_init.vhd
- xlclockdriver_rd.vhd
- framing.vhd
- README
- ssrfft_8x256_sync.vhd
- tb.vhd
- tlast_gen.vhd
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- fir_0.coe
- fir_1.coe
- fir_2.coe
- fir_3.coe
- fir_4.coe
- fir_5.coe
- fir_6.coe
- fir_7.coe
- fir_0.xci
- fir_1.xci
- fir_2.xci
- fir_3.xci
- fir_4.xci
- fir_5.xci
- fir_6.xci
- fir_7.xci
- fir.tcl.template
- ipgen.tcl
- add.tcl
- fir.tcl
- fir_0.veo
- gen.pl
- Makefile
- cascaded_channelizer.m
- filter_design.m
- gen_coeffs_multilane_analysis.m
- tb.sv
- axi_slv.vhd
- axis_pfba_pr_4x256_v1.sv
- firs.sv
- pfb.sv
- pfb_cfg.vhd
- pfb_ctrl.vhd
- pfb_ctrl_pkg.vhd
- pfb_framing.vhd
- pfb_reorder.sv
- pfb_swap.sv
- pfb_switch.v
- pimod_pfb.vhd
- zn_nb.vhd
- axis_pfba_pr_4x256_v1_v1_0.tcl
- component.xml
- README
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- conv_pkg.vhd
- single_reg_w_init.vhd
- srl17e.vhd
- srl33e.vhd
- ssr_8x256.vhd
- ssr_8x256_entity_declarations.vhd
- synth_reg.vhd
- synth_reg_reg.vhd
- synth_reg_w_init.vhd
- xlclockdriver_rd.vhd
- framing.vhd
- README
- ssrfft_8x256_sync.vhd
- tb.vhd
- tlast_gen.vhd
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- fir_0.coe
- fir_1.coe
- fir_2.coe
- fir_3.coe
- fir_4.coe
- fir_5.coe
- fir_6.coe
- fir_7.coe
- fir_0.xci
- fir_1.xci
- fir_2.xci
- fir_3.xci
- fir_4.xci
- fir_5.xci
- fir_6.xci
- fir_7.xci
- fir.tcl.template
- ipgen.tcl
- add.tcl
- fir.tcl
- fir_0.veo
- gen.pl
- Makefile
- cascaded_channelizer.m
- filter_design.m
- gen_coeffs_multilane_synthesis.m
- tb.sv
- tb_pfb.sv
- tb_switch.sv
- axi_slv.vhd
- axis_pfbs_pr_4x256_v1.sv
- firs.sv
- pfb.sv
- pfb_cfg.vhd
- pfb_conjugate.sv
- pfb_ctrl.vhd
- pfb_ctrl_pkg.vhd
- pfb_framing.vhd
- pfb_reorder.sv
- pfb_swap.sv
- pfb_switch.v
- pimod_pfb.vhd
- zn_nb.vhd
- axis_pfbs_pr_4x256_v1_v1_0.tcl
- component.xml
- README
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- dds_compiler_0.veo
- dds_compiler_0.vho
- dds_compiler_0.xci
- dds_compiler_0.xml
- fir_compiler_0.veo
- fir_compiler_0.vho
- fir_compiler_0.xci
- fir_compiler_0.xml
- data_iq.txt
- tb.sv
- tb_ctrl.v
- tb_down_conversion.sv
- tb_down_conversion_fir.sv
- tb_fir.sv
- axi_slv.vhd
- axis_readout_v1.v
- ctrl.sv
- down_conversion.v
- down_conversion_fir.v
- fir.coe
- readout_top.v
- axis_readout_v1_v1_0.tcl
- component.xml
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- dds_compiler_0.veo
- dds_compiler_0.vho
- dds_compiler_0.xci
- dds_compiler_0.xml
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- fir_compiler_0.veo
- fir_compiler_0.vho
- fir_compiler_0.xci
- fir_compiler_0.xml
- data_iq.txt
- dout.csv
- dout_fs.csv
- tb.sv
- axi_slv.vhd
- axis_readout_v2.v
- ctrl.sv
- down_conversion.v
- down_conversion_fir.v
- fir.coe
- fir_compiler_0.v
- readout_top.v
- synchronizer_n.vhd
- axis_readout_v2_v1_0.tcl
- component.xml
- dds_0.xci
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- fir_0.xci
- fir.coe
- fir_0.v
- fir_0.veo
- tb.sv
- tb_down_conversion.sv
- axis_readout_v3.v
- ctrl.sv
- down_conversion.sv
- down_conversion_fir.sv
- latency_reg.v
- axis_readout_v3_v1_0.tcl
- component.xml
- axis_register_slice_nb.vhd
- tb.vhd
- axis_register_slice_nb_v1_0.tcl
- component.xml
- axis_reorder_iq_v1.sv
- tb.sv
- axis_reorder_iq_v1_v1_0.tcl
- component.xml
- axis_resampler_2x1_v1.sv
- tb.sv
- axis_resampler_2x1_v1_v1_0.tcl
- axis_resampler_2x1_v1_0.xcix
- component.xml
- axis_set_reg.vhd
- axis_set_reg_v1_0.tcl
- component.xml
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- dds_compiler_0.veo
- dds_compiler_0.vho
- dds_compiler_0.xci
- dds_compiler_0.xml
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- fir_0.coe
- fir_0.veo
- fir_0.vho
- fir_0.xci
- fir_0.xml
- gen_gauss.py
- tb.sv
- tb_dds.sv
- tb_fir.sv
- tb_latency_reg.sv
- tb_signal_gen_top.sv
- axi_slv.vhd
- axis_sg_int4_v1.v
- bram.v
- ctrl.sv
- data_writer.vhd
- latency_reg.v
- signal_gen.v
- signal_gen_top.v
- synchronizer_n.vhd
- axis_sg_int4_v1_v1_0.tcl
- component.xml
- dds_compiler_0.xci
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- fir_0.coe
- fir_0.xci
- axi_slv.vhd
- axis_sg_int4_v2.v
- bram.v
- ctrl.sv
- data_writer.vhd
- latency_reg.v
- signal_gen.v
- signal_gen_top.v
- synchronizer_n.vhd
- axis_sg_int4_v2_v1_0.tcl
- component.xml
- dds_compiler_0.xci
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- tb.sv
- axi_slv.v
- axis_sg_mixmux8_v1.v
- ctrl.sv
- dds_top.v
- latency_reg.v
- mult_32x32.v
- phase_ctrl.sv
- sg_mux8.v
- synchronizer_n.vhd
- axis_sg_mixmux8_v1_v1_0.tcl
- component.xml
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- dds_compiler_0.veo
- dds_compiler_0.vho
- dds_compiler_0.xci
- dds_compiler_0.xml
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- dout.csv
- tb.sv
- tb_ctrl.sv
- tb_dds_top.sv
- tb_sg_mux4.sv
- axi_slv.vhd
- axis_sg_mux4.v
- ctrl.sv
- dds_top.v
- latency_reg.v
- phase_ctrl.sv
- sg_mux4.v
- synchronizer_n.vhd
- axis_sg_mux4_v1_v1_0.tcl
- component.xml
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- dds_compiler_0.veo
- dds_compiler_0.vho
- dds_compiler_0.xci
- dds_compiler_0.xml
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- tb.sv
- axi_slv.vhd
- axis_sg_mux4.v
- ctrl.sv
- dds_top.v
- latency_reg.v
- phase_ctrl.sv
- sg_mux4.v
- synchronizer_n.vhd
- axis_sg_mux4_v1_v1_0.tcl
- axis_sg_mux4_v2_v1_0.tcl
- component.xml
- dds_compiler_0.xci
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- tb.sv
- axi_mst_0.xcix
- axi_slv.vhd
- axis_sg_mux4_v3.v
- ctrl.sv
- dds_top.v
- latency_reg.v
- phase_ctrl.sv
- sg_mux4.v
- synchronizer_n.vhd
- axis_sg_mux4_v3_v1_0.tcl
- component.xml
- dds_compiler_0.xci
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- top_sg_mux8.xdc
- tb.sv
- tb_dds.sv
- tb_dds_top.sv
- axi_mst_0.xcix
- axi_slv.v
- axis_sg_mux8_v1.v
- ctrl.sv
- dds_top.v
- latency_reg.v
- mult_32x32.v
- phase_ctrl.sv
- sg_mux8.v
- synchronizer_n.vhd
- axis_sg_mux8_v1_v1_0.tcl
- component.xml
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- dds_compiler_0.veo
- dds_compiler_0.vho
- dds_compiler_0.xci
- dds_compiler_0.xml
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- gauss.txt
- gen_gauss.py
- gen_ramp.py
- ramp.txt
- tb.sv
- tb_ctrl.v
- tb_dds.v
- tb_signal_gen.sv
- tb_signal_gen_top.sv
- axi_slv.vhd
- axis_signal_gen_v4.v
- bram.v
- ctrl.sv
- data_writer.vhd
- dither.v
- random_gen.v
- signal_gen.v
- signal_gen_top.v
- synchronizer_n.vhd
- axis_signal_gen_v4_v1_0.tcl
- component.xml
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- dds_compiler_0.veo
- dds_compiler_0.vho
- dds_compiler_0.xci
- dds_compiler_0.xml
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- dout.csv
- gauss.txt
- gen_gauss.py
- tb.sv
- tb_ctrl.v
- tb_dds.v
- tb_signal_gen.sv
- tb_signal_gen_top.sv
- axi_slv.vhd
- axis_signal_gen_v5.v
- bram.v
- ctrl.sv
- data_writer.vhd
- latency_reg.v
- signal_gen.v
- signal_gen_top.v
- synchronizer_n.vhd
- axis_signal_gen_v5_v1_0.tcl
- component.xml
- README
- dds_compiler_0.veo
- dds_compiler_0.vho
- dds_compiler_0.xci
- dds_compiler_0.xml
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- axi_mst_0_ooc.xdc
- gauss.txt
- gen_gauss.py
- tb.sv
- tb_behav_waves.wcfg
- tb_ctrl.sv
- axi_slv_sg_v6.vhd
- axis_signal_gen_v6.v
- ctrl_sg_v6.sv
- data_writer.vhd
- latency_reg.v
- signal_gen.v
- signal_gen_ooc.xdc
- signal_gen_top.v
- signal_gen_v6.xdc
- synchronizer_n.vhd
- timing.xdc
- axis_signal_gen_v6_v1_0.tcl
- component.xml
- README
- axis_terminator.vhd
- axis_terminator_v1_0.tcl
- component.xml
- axis_tmux_v1.sv
- tb.sv
- tmux.sv
- axis_tmux_v1_v1_0.tcl
- axis_tmux_v1_0.xcix
- component.xml
- alu.v
- bitw.vhd
- math.vhd
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- axis_mst_0.veo
- axis_mst_0.vho
- axis_mst_0.xci
- axis_mst_0.xml
- axis_slv_0.veo
- axis_slv_0.vho
- axis_slv_0.xci
- axis_slv_0.xml
- axis_read.v
- axis_write.v
- data_mem.v
- data_mem_ctrl.v
- mem_rw.v
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- gen_sim.sv
- regfile.vhd
- regfile_8p.vhd
- compile.pl
- prog.asm
- prog.asm.old
- prog.bin
- prog.bin-dump
- tb.sv
- tb_alu.sv
- axi_slv_custom.sv
- axis_tproc64x32_x8.v
- bram.v
- bram.vhd
- cond.vhd
- ctrl.sv
- s_axis_read.vhd
- stack.vhd
- synchronizer_n.vhd
- timed_ictrl.vhd
- tproc64x32_x8.v
- axis_tproc64x32_x8_v1_0.tcl
- component.xml
- axi_vip_v1_1_changelog.txt
- axi_infrastructure_v1_1_0.vh
- axi_infrastructure_v1_1_vl_rfs.v
- axi_vip_v1_1_vl_rfs.sv
- axi_vip_v1_1_vlsyn_rfs.sv
- axi_mst_0.cpp
- axi_mst_0.h
- axi_mst_0.sv
- axi_mst_0_pkg.sv
- axi_mst_0_sc.cpp
- axi_mst_0_sc.h
- axi_mst_0_stub.sv
- axi_mst_0.sv
- axi_vip.cpp
- axi_vip.h
- sim_ipc_aximm_master.cpp
- sim_ipc_aximm_master.h
- sim_ipc_aximm_slave.cpp
- sim_ipc_aximm_slave.h
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- axi_mst_0_ooc.xdc
- dsp_macro_0.xci
- bin2gray.vhd
- bram_dp.vhd
- bram_simple_dp.vhd
- fifo.vhd
- fifo_axi.vhd
- fifo_dc.vhd
- gray2bin.vhd
- rd2axi.vhd
- synchronizer_vect.vhd
- data_iq.txt
- gauss.txt
- tb.sv
- tb_avg.sv
- tb_avg_buffer.sv
- tb_avg_top.sv
- tb_buffer.sv
- tb_buffer_top.sv
- avg.sv
- avg_buffer.v
- avg_top.v
- axi_slv.vhd
- axis_weighted_buffer.v
- buffer.sv
- buffer_top.v
- data_reader.vhd
- data_writer.vhd
- matched_filter.vhd
- outreg.sv
- synchronizer_n.vhd
- axis_weighted_buffer_v1_3.tcl
- component.xml
- axi4stream_vip_0.vho
- axi4stream_vip_0.xci
- axi4stream_vip_0.xml
- axi4stream_vip_1.vho
- axi4stream_vip_1.xci
- axi4stream_vip_1.xml
- axi_vip_0.vho
- axi_vip_0.xci
- axi_vip_0.xml
- tb.sv
- tb_behav_waves.wcfg
- bram_dp.vhd
- data_reader.vhd
- data_writer.vhd
- fifo.vhd
- mr_buffer.vhd
- mr_buffer_v1_0.vhd
- mr_buffer_v1_0_S00_AXI.vhd
- synchronizer.vhd
- mr_buffer_et_v1_0.tcl
- mr_buffer_et_v1_1.tcl
- component.xml
- tb_behav.wcfg
- tb_qcom.sv
- _qcom_ips.sv
- axi_qick_com.sv
- axi_slv_qcom.vhd
- qcom_link.sv
- qick_cmd.sv
- qick_com.sv
- axis_qick_com_v1_0.tcl
- qick_com_v1_0.tcl
- component.xml
- Debug_Core.xml
- Debug_Core_rtl.xml
- qick_peripheral.xml
- qick_peripheral_rtl.xml
- qick_qproc_ctrl.xml
- qick_qproc_ctrl_rtl.xml
- qproc_time_ctrl.xml
- qproc_time_ctrl_rtl.xml
- tb_enc.sv
- tb_periph.sv
- _qp_ips.sv
- axi_qick_peripheral.sv
- axi_slv_qp.vhd
- qick_periph.sv
- axis_qick_com_v1_0.tcl
- qick_com_v1_0.tcl
- qick_peripheral_v1_0.tcl
- component.xml
- dsp_macro_0.xci
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- dmem_issue35.mem
- prog.bin
- prog_issue35.mem
- tb_axis_qick_processor.sv
- tb_qick_processor_issue35.sv
- tb_qproc.wcfg
- tb_qproc_issue35.wcfg
- tb_qproc_issue37.wcfg
- wave.bin
- wave_issue35.mem
- _qproc_defines.svh
- _qproc_ips.sv
- axi_slv_qproc.vhd
- axis_qick_processor.sv
- axis_read.v
- axis_write.v
- data_mem_ctrl.v
- logoQICK_128x128.png
- mem_rw.v
- qcore_cpu.sv
- qcore_ctrl_hazard.sv
- qcore_mem.v
- qcore_reg_bank.sv
- qick_processor.sv
- qick_processor.xdc
- qick_processor_ooc.xdc
- qproc_axi_reg.sv
- qproc_core.sv
- qproc_ctrl.sv
- qproc_dispatcher.sv
- qproc_inport_reg.sv
- qproc_mem_ctrl.v
- qproc_time_ctrl.sv
- qick_processor_v2_0.tcl
- component.xml
- sg_translator.v
- qick_sg_translator_v1_0.tcl
- sg_translator_v1_0.tcl
- component.xml
- axi_mst_0.xci
- tb_fifo_dma.sv
- tb_fifo_dma_behav.wcfg
- tb_qtag.sv
- tb_qtag_behav.wcfg
- tb_qtt_cmp.sv
- tb_qtt_cmp_behav.wcfg
- tb_smp_fifo.sv
- tb_smp_fifo.wcfg
- tb_tag_fifo.sv
- tb_tag_fifo.wcfg
- thr_cmp.sv
- _qtt_dma.sv
- _qtt_ips.sv
- _qtt_mem.sv
- axi_qick_time_tagger.sv
- axi_slv_qtt.vhd
- qick_time_tagger.sv
- qtt_cmd.sv
- qtt_tag_calc.sv
- smp_mem.sv
- tag_gen.sv
- tag_mem.sv
- axi_qick_time_tagger_v1_0.tcl
- qick_time_tagger_v1_0.tcl
- component.xml
- qick_vect2bits_v1_0.gtcl
- qick_vec2bit.v
- qick_vect2bits.v
- qick_vec2bit_v1_0.tcl
- qick_vec2bits_v1_0.tcl
- qick_vect2bits_v1_0.tcl
- component.xml
- README.md
- RB_tProc_v1_experiment.ipynb
- RB_tProc_v2_experiment.ipynb
- test01_basic_multipulse.ipynb
- tests_generator.ipynb
- qick_111_rfbv1.bit
- qick_111_rfbv1.hwh
- qick_111_rfbv1.ltx
- bd_2020-2.tcl
- ios.xdc
- proj.tcl
- timing.xdc
- qick_111_rfbv2.bit
- qick_111_rfbv2.hwh
- qick_111_rfbv2.ltx
- bd_2020-2.tcl
- ios.xdc
- proj.tcl
- timing.xdc
- qick_111.bit
- qick_111.hwh
- qick_111.ltx
- bd_2022-1.tcl
- ios.xdc
- proj.tcl
- timing.xdc
- qick_216.bit
- qick_216.hwh
- qick_216.ltx
- bd_2022-1.tcl
- ios.xdc
- proj.tcl
- timing.xdc
- qick_4x2.bit
- qick_4x2.hwh
- qick_4x2.ltx
- bd_2022-1.tcl
- ios.xdc
- proj.tcl
- timing.xdc
- qick_111.bit
- qick_111.hwh
- qick_111.ltx
- bd_2023-1.tcl
- ios.xdc
- proj.tcl
- timing.xdc
- qick_216.bit
- qick_216.hwh
- qick_216.ltx
- bd_2023-1.tcl
- ios.xdc
- proj.tcl
- timing.xdc
- qick_216_rfbv2.bit
- qick_216_rfbv2.hwh
- qick_216_rfbv2.ltx
- bd_2023-1.tcl
- ios.xdc
- proj.tcl
- timing.xdc
- qick_216.bit
- qick_216.hwh
- qick_216.ltx
- bd_2023-1.tcl
- ios.xdc
- proj.tcl
- timing.xdc
- qick_4x2.bit
- qick_4x2.hwh
- qick_4x2.ltx
- bd_2023-1.tcl
- ios.xdc
- proj.tcl
- timing.xdc
- axi_mst_0.veo
- axi_mst_0.vho
- axi_mst_0.xci
- axi_mst_0.xml
- axi_mst_0_ooc.xdc
- dmem.mem
- pmem.mem
- README
- sg_0.mem
- wmem.mem
- dmem.mem
- pmem.mem
- README
- sg_0.mem
- wmem.mem
- dmem.mem
- pmem.mem
- README
- sg_0.mem
- wmem.mem
- dmem.mem
- pmem.mem
- README
- sg_0.mem
- wmem.mem
- dmem.mem
- pmem.mem
- sg_0.mem
- wmem.mem
- dmem.mem
- pmem.mem
- README
- sg_0.mem
- wmem.mem
- dmem.mem
- pmem.mem
- README
- sg_0.mem
- wmem.mem
- dmem.mem
- pmem.mem
- README
- sg_0.mem
- wmem.mem
- dmem.mem
- pmem.mem
- README
- sg_0.mem
- wmem.mem
- model_DAC_ADC.sv
- qick_dut.sv
- tb_qick.sv
- tb_qick_behav.wcfg
- tb_qick_stimuli.svh
- tb_qick_tasks.svh
- qick_testbench.xpr
- soccfg.json
- .gitignore
- README.md
- tProcessor_64_and_Signal_Generator_V4.pdf
- logoQICK.svg
- QCE2023_banner.svg
- QICK.jpg
- qsystem-readout.png
- qsystem-readout.svg
- ZCU216Board.jpg
- RF Board Schematic V1.pdf
- README.md
- RF Board Schematic V2.pdf
- RF_Gen4.zip
- README.md
- 00_nameserver.ipynb
- 01_server.ipynb
- 02_client.ipynb
- nameserver.sh
- pyro_service.py
- qick_pyro.service
- Conditional_False_Pulse.pdf
- Conditional_True_NoPulse.pdf
- Gain_sweep.pdf
- Gain_sweep_python.pdf
- Phase_calibration.pdf
- Phase_sweep.pdf
- QICK_wiring_new.png
- 000_Install_qick_package.ipynb
- 00_Send_receive_pulse.ipynb
- 01_phase_calibration.asm
- 01_Phase_coherent_readout.ipynb
- 02_Sweeping_variables.ipynb
- 03_Conditional_logic.ipynb
- 04_Reading_Math_Writing.ipynb
- 05_PhaseCoherence_QickProgram.ipynb
- 06_qubit_demos.ipynb
- 07_Sweep_ND_variables.ipynb
- 08_Special_buffers.ipynb
- 09_photon_counting.ipynb
- README.md
- sds_trace_data.dat
- __init__.py
- generator.py
- peripherals.py
- readout.py
- tproc.py
- xcom.py
- dataconverter_clocking_overview.png
- dataconverter_context.png
- LMX2594_REF-245M76__OUT-0204M80_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-0245M76_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-0491M52_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-1024M00_11052019_D.txt
- LMX2594_REF-245M76__OUT-1966M08_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-2211M84_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-2457M60_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-3072M00_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-3932M16_10172019_I.txt
- LMX2594_REF-245M76__OUT-4096M00_11052019_D.txt
- LMX2594_REF-245M76__OUT-4423M68_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-4915M20_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-5898M24_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-6144M00_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-6881M28_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-7372M80_10172019_I_D.txt
- LMX2594_REF-245M76__OUT-7864M32_10172019_I.txt
- LMX2594_REF-245M76__OUT-8192M00_11052019.txt
- LMX2594_REF-245M76__OUT-8847M36_10172019_I.txt
- LMX2594_REF-245M76__OUT-9830M40_10172019_I.txt
- lmk04828b_regdump_defaults.txt
- lmk04828b_regmap.json
- lmx2594_regmap.json
- xrfdc_cdefs.h
- __init__.py
- boards.py
- clock_models.py
- data_processing.py
- spidev.py
- clockfile.txt
- clockfile_out.txt
- lmk04828b_regmap.json
- lmk04828b_regmap.txt
- lmk04828b_regmap_fix.json
- lmx2594.txt
- lmx2594_regmap.json
- lmx2594_regmap_out.json
- regmap_creation.ipynb
- regmap_parsing.ipynb
- .gitignore
- LICENSE
- MANIFEST.in
- README.md
- setup.py
- __init__.py
- asm_v1.py
- asm_v2.py
- averager_program.py
- helpers.py
- ip.py
- parser.py
- pyro.py
- pyro_cli.py
- qick.py
- qick_111.bit
- qick_111.hwh
- qick_216.bit
- qick_216.hwh
- qick_4x2.bit
- qick_4x2.hwh
- qick_asm.py
- rfboard.py
- streamer.py
- tprocv2_assembler.py
- VERSION
- .gitignore
- .readthedocs.yaml
- CITATION.cff
- LICENSE
- README.md
- setup.py
# 설치 가이드
1. 코드 내려받기
git clone https://github.com/openquantumhardware/qick
깃허브에서 프로젝트 코드 전체를 내 컴퓨터로 내려받습니다.
cd qick
방금 내려받은 프로젝트 폴더 안으로 이동합니다.
2. Python
쉬움 추천사전 준비물
pip install .
PyPI에 배포된 패키지를 바로 설치합니다. 소스 클론이 필요 없습니다.
jupyter notebook
브라우저에서 노트북(.ipynb) 파일들을 열람하고 실행할 수 있는 Jupyter 화면을 켭니다.
에러 메시지 없이 실행되고 터미널에 안내 문구가 출력되면 정상입니다.
3. Make
보통사전 준비물
- Git GitHub에서 프로젝트 코드를 내려받으려면 필요합니다.
- Make Linux/macOS는 보통 기본 설치되어 있습니다. Windows는 별도 설치(예: MSYS2, WSL)가 필요합니다.
⚠️ 이 프로젝트는 규모가 큰 저장소라, 이 방법이 실제 핵심 제품이 아니라 내부 하위 패키지를 가리키는 것일 수 있습니다. README 전체를 함께 확인해보세요.
cd firmware/ip/axis_pfb_readout_v2/src/fir
이 프로젝트의 관련 파일이 하위 폴더 안에 있어서, 먼저 그 폴더로 이동합니다.
make
생성된 빌드 설정을 바탕으로 실제 컴파일을 진행해 실행 파일을 만듭니다.
에러 없이 끝나면 성공입니다. 생성된 실행 파일을 직접 실행해보세요.
// repository documentation
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