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mips-cpu
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A MIPS CPU implemented in Verilog
Download README (.md)
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# mips-cpu A MIPS CPU implemented in Verilog This is a course project of ACM Honored Class @ SJTU ([wiki](https://acm.sjtu.edu.cn/wiki/System_2017)) ## Features - 32-bit MIPS instruction - 5-stage pipeline - set-associative cache - runnable on FPGA (tested on XC7A35T) - memory simulated by C++ program (use UART)
