Architecture-of-CPU-projects

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Architecture-of-CPU-projects

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VHDL , ModelSIM, Quartus, FPGA, Image Processing

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# Architecture of CPU course projects
#

## LAB 1 - Designing a basic ALU
![alt text](https://image.ibb.co/kY92CS/1.png)
#### The aims of this laboratory are to obtaining basic skills in VHDL and ModelSim, General knowledge rehearsal in digital systems and proper analysis and understanding of architecture design.
#### Full Description in English - <a href="https://github.com/MaorAssayag/Architecture-of-CPU-projects/blob/master/Designing%20a%20basic%20ALU/readme.pdf">link</a>
#

## LAB 2 - Designing a basic ALU with FloatingPoint Unit & FPGA with QUARTUS
![alt text](https://github.com/MaorAssayag/Architecture-of-CPU-projects/blob/master/Designing%20ALU%20with%20FPU%20to%20FPGA/DOC/Critical%20Path%20png/system.PNG)
#### The aims of this laboratory are to Obtaining basic skills in VHDL and ModelSim, General knowledge rehearsal in digital systems, proper analysis and understanding of architecture design, Understanding arithmetic synthesis and FPGA arithmetic limitations and Floating-point design.
#### Full Description in English - <a href="https://github.com/MaorAssayag/Architecture-of-CPU-projects/blob/master/Designing%20ALU%20with%20FPU%20to%20FPGA/readme.pdf">link</a>

#

## LAB 3 - Designing pipelined MIPS on FPGA
![alt text](https://upload.wikimedia.org/wikipedia/commons/9/9e/Pipeline_MIPS.png)
#### The aim of this laboratory is to design a simple MIPS compatible CPU. The CPU will use a PIPELINED architecture and must be capable of performing instructions from MIPS instruction set. The design will be executed on the Altera Board. The MIPS architecture is Harvard architecture in order to increase throughput and simplify the logic. There is need to implement floating point instructions (ADD, SUB and MUL from previous work) and floating-point register file.

#### Full Description in English - <a href="https://github.com/MaorAssayag/Architecture-of-CPU-projects/blob/master/Designing%20Pipelined%20MIPS%20on%20FPGA/readme.pdf">link</a>

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# Final Project - Image Processing on FPGA
![alt text](https://github.com/MaorAssayag/Architecture-of-CPU-projects/blob/master/Image%20Processing%20on%20FPGA/DOC/diagram.PNG)
#### Design a Real Time entropy detection filter for an image received from a camera. The histogram of the image must be calculated.

#### Full Description in English - <a href="https://github.com/MaorAssayag/Architecture-of-CPU-projects/blob/master/Image%20Processing%20on%20FPGA/readme.pdf">link</a>

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