gcnn-dvs-fpga

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Hardware Acceleration of Neural Networks for Event Camera-Based Object Detection on SoC FPGAs

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# Embedded graph convolutional networks for real-time event data processing on SoC FPGAs

This repository provides the first hardware module for acceleration of Graph Convolutional Neural Network for Event Data processing on SoC FPGA. The solution deployed for the Zynq UltraScale+ MPSoC ZCU104 platform was evaluated for objects classification for the MNIST-DVS and N-Cars datasets. The system is implemented using the SystemVerilog language and the Vitis/Vivado 2022.2 environment.

<div align="center">
  <img src="assets/Diagram.png" width="1000px"/><br>
    <p style="font-size:1.5vw;">We present the hardware architecture as a pipeline of modules that process event data in a completely parallel manner. The system consists of two parts -- asynchronous (operating in an event-by-event manner) and synchronous, in which operations are performed on sub-graphs. </p>
</div>

## Authors

## AMD Open Hardware Desigh Competition 2024

We were awarded the title of winner in PhD Categorie

## Getting Started

The project is divided into two parts: Software and Hardware. For more information, please refer to the README files in the `SW`, `HW` and `demo` folders.

### Software

The software part of the project is responsible for evaluating models and preprocessing datasets that are used in Hardware part. The software part is located in the `SW` folder.

### Hardware

The hardware part of the project is responsible for implementing the Graph Convolutional Neural Network on the FPGA. The hardware part is located in the `HW` folder.

### Demo

The `demo` folder provides all files necessary for running the MNIST-DVS classification demo for GCNNs inference with Zynq UltraScale+ MPSoC ZCU104 Evaluation Kit.

## Citation
If you find this project useful in your research, please consider citing our work:

```BibTeX
@article{jeziorek2026embedded,
  title={Embedded Graph Convolutional Networks for Real-Time Event Data Processing on SoC FPGAs},
  author={Jeziorek, Kamil and Wzorek, Piotr and Blachut, Krzysztof and Pinna, Andrea and Kryjak, Tomasz},
  journal={Journal of Systems Architecture},
  doi = {https://doi.org/10.1016/j.sysarc.2026.103850},
  url = {https://www.sciencedirect.com/science/article/pii/S1383762126001682},
  year={2026}
}

@article{jeziorek2024optimising,
  title={Optimising graph representation for hardware implementation of graph convolutional networks for event-based vision},
  author={Jeziorek, Kamil and Wzorek, Piotr and Blachut, Krzysztof and Pinna, Andrea and Kryjak, Tomasz},
  booktitle={International Workshop on Design and Architecture for Signal and Image Processing},
  pages={110--122},
  year={2024},
  organization={Springer}
}

@inproceedings{jeziorek2023memory,
  title={Memory-efficient graph convolutional networks for object classification and detection with event cameras},
  author={Jeziorek, Kamil and Pinna, Andrea and Kryjak, Tomasz},
  booktitle={2023 Signal Processing: Algorithms, Architectures, Arrangements, and Applications (SPA)},
  pages={160--165},
  year={2023},
  organization={IEEE}
}
```

gcnn-dvs-fpga

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