system-verilog-for-design-and-verification

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# SystemVerilog for Design and Verification

## Introduction
These labs tasks are part of the Cadence training course [SystemVerilog for Design and Verification](https://www.cadence.com/en_US/home/training/all-courses/82143.html) and demonstrate the use of SystemVerilog language constructs to complete simple, common design tasks.

## Labs

|  Lab  | Name | Objective |
| :---: | :--- | :-------- |
| 1 | [Modeling a Simple Register](https://github.com/usman1515/SystemVerilog-for-Design-and-Verification/tree/master/lab_1) | To use SystemVerilog procedural constructs to model a simple register. |
| 2 | [Modeling a Simple Multiplexor](https://github.com/usman1515/SystemVerilog-for-Design-and-Verification/tree/master/lab_2) | To use SystemVerilog procedural constructs to model a simple multiplexor. |
| 3 | [Modeling a Simple Counter](https://github.com/usman1515/SystemVerilog-for-Design-and-Verification/tree/master/lab_3) | To use SystemVerilog procedural constructs and operators to model a simple counter. |
| 4 | [Modeling a Sequence Controller](https://github.com/usman1515/SystemVerilog-for-Design-and-Verification/tree/master/lab_4) | To use SystemVerilog user-defined types, procedural statements and operators to model a state machine. |
| 5 | [Modeling an Arithmetic Logic Unit (ALU)](https://github.com/usman1515/SystemVerilog-for-Design-and-Verification/tree/master/lab_5) | To use SystemVerilog user-defined types, procedural statements, and operators to model an ALU. |
| 6 | [Testing a Memory Module](https://github.com/usman1515/SystemVerilog-for-Design-and-Verification/tree/master/lab_6) | To use SystemVerilog subprogram enhancements to test a memory module. |

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