31-Days-of-Daily-Verilog-Programming-Challenge

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31-Days-of-Daily-Verilog-Programming-Challenge

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In LinkedIn I took a challenge called " #DailyVerilogProgrammingChallenge " which I did consistently with an aim to do Verilog Coding straight for 31 days. So, this repository is all about the 31 Verilog Codes, Testbenches, Simulation and Schematic Result.

31-Days-of-Daily-Verilog-Programming-Challenge 최신버젼 다운로드

최종 버전 다운로드 (.zip)

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# Daily Verilog Programming Challenge

### Overview

Welcome to the **Daily Verilog Programming Challenge** repository! Over the course of 31 days, I started my journey to enhance Verilog programming skills using Xilinx Vivado 2023.1 version Tool. This challenge was designed to strngthen my foundation in digital design and Verilog HDL by solving a variety of Verilog problems on a daily basis. What started as a daunting task soon turned into an engaging and rewarding experience, fostering consistency, discipline, and a deeper understanding of Verilog.

### Challenge Highlights

- **Duration:** 31 Days
- **Tools Used:** Xilinx Vivado Tool
- **Focus Areas:** Basic Verilog programming, combinational and sequential circuits, testbench creation, simulation, and synthesis.
- **Goals:**
  - Develop a strong foundation in Verilog HDL.
  - Gain proficiency in using Xilinx Vivado for design and simulation.
  - Build a habit of daily coding and problem-solving.
  - Engage with the community and share knowledge.

### Repository Structure

This repository is organized into folders for each day of the challenge, containing the problem statements, Verilog code, and testbenches. Each folder includes:

- **Verilog Code:** The Verilog implementation of the solution. 
- **Testbench:** The testbench used to validate the solution.
- **Simulation Results:** Screenshots of the simulation results (where applicable).
- **Schematic Result:** Schematic view of the Design.

### What it contains

[Day 1 - And Gate](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%201%20-%20And%20Gate)

[Day 2 - Or Gate](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%202%20-%20Or%20Gate)

[Day 3 - Not Gate](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%203%20-%20Not%20Gate)

[Day 4 - Nand Gate](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%204%20-%20Nand%20Gate)

[Day 5 - Nor Gate](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%205%20-%20Nor%20Gate)

[Day 6 - Xor Gate](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%206%20-%20Xor%20Gate)

[Day 7 - Xnor Gate](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%207%20-%20Xnor%20Gate)

[Day 8 - Full Adder](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%208%20-%20Full%20Adder)

[Day 9 - ripple carry adder](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%209%20-%20ripple%20carry%20adder)

[Day 10 - Carry look ahead adder](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2010%20-%20Carry%20look%20ahead%20adder)

[Day 11 - Carry Skip Adder](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2011%20-%20Carry%20Skip%20Adder)

[Day 12 - Carry Increment Adder](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2012%20-%20Carry%20Increment%20Adder)

[Day 13 - Carry Save Adder](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2013%20-%20Carry%20Save%20Adder)

[Day 14 - Full Subtractor](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2014%20-%20Full%20Subtractor)

[Day 15 - Ripple Carry Subtractor](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2015%20-%20Ripple%20Carry%20Subtractor)

[Day 16 - Multiplexer](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2016%20-%20Multiplexer)

[Day 17 - Demultiplexer](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2017%20-%20Demultiplexer)

[Day 18 - D Flip Flop](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2018%20-%20D%20Flip%20Flop)

[Day 19 - T Flip Flop](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2019%20-%20T%20Flip%20Flop)

[Day 20 - JK Flip Flop](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2020%20-%20JK%20Flip%20Flop)

[Day 21 - SR Flip Flop](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2021%20-%20SR%20Flip%20Flop)

[Day 22 - SR Latch](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2022%20-%20SR%20Latch)

[Day 23 - D Latch](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2023%20-%20D%20Latch)

[Day 24 - Decoder](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2024%20-%20Decoder)

[Day 25 - Encoder](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2025%20-%20Encoder)

[Day 26 - Up Counter](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2026%20-%20Up%20Counter)

[Day 27 - Down Counter](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2027%20-%20Down%20Counter)

[Day 28 - UpDown Counter](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2028%20-%20UpDown%20Counter)

[Day 29 - Asynchronous Counter](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2029%20-%20Asynchronous%20Counter)

[Day 30 - Binary to Gray Code](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2030%20-%20Binary%20to%20Gray%20Code)

[Day 31 - Gray to Binary Code](https://github.com/EkthaReddy/31-Days-of-Daily-Verilog-Programming-Challenge/tree/main/Day%2031%20-%20Gray%20to%20Binary%20Code)

## Contribution and Suggestions

I am always looking to grow and improve. If you have any suggestions for topics, projects, or areas of focus that would help me in my journey, please feel free to open an issue or contribute to the repository. Your insights and feedback are invaluable.

## Connect with Me

- **LinkedIn:** [www.linkedin.com/in/ekthareddy](#)
- **Email:** [reddyektha1@gmail.com](#)

Thank you for visiting my repository. I hope you find these Verilog programming exercises as insightful and enjoyable as I did. Happy coding!

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