YAEmulator-GB-Rust

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YAEmulator-GB-Rust

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Yet Another Emulator - Rust edition. Learning Rust with GB Emulator

YAEmulator-GB-Rust 최신버젼 다운로드

최종 버전 다운로드 (.zip)

// repository documentation

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# YAEmulator-Rust

## GB Structure
![GB Structure](https://raw.githubusercontent.com/alessandrome/YAEmulator-GB-Rust/main/GB_Schema.png)

## GB Memory Map
![Memory Map](https://raw.githubusercontent.com/alessandrome/YAEmulator-GB-Rust/main/Memory_Map.png)

## Status
CPU and PPU are doing their work as expected. Need to add real user inputs and then audio. Note that this not work directly with cmd pixel but with special characters (using low font size as 4px)
![Super Mario first frame](https://raw.githubusercontent.com/alessandrome/YAEmulator-GB-Rust/main/Super_Mario_frame_cmd.png)

## References
[GBDev.io](https://gbdev.io/pandocs/About.html) - Main general references for GB/GBC hardware

[Game Boy Official Programming Manual](https://ia903208.us.archive.org/9/items/GameBoyProgManVer1.1/GameBoyProgManVer1.1.pdf) - Official Nintendo documentation about GB (v 1.1). Thank you archive.org

[Copetti](https://www.copetti.org/writings/consoles/game-boy/) - Lite reading about GB/GBC hardware functionalities

[Rylev DMG-01](https://rylev.github.io/DMG-01/public/book/introduction.html) - Secondary reference about how a Game Boy works

# Important Things
## Address Bus Latch, IDU and Address Buffer Timing

One of the most non-obvious behaviors of the CPU is that the address bus has not an independent Address register, but the
address bus is switched between a 16-bit register as needed, maybe through a Mux.

You can think it is like a train binary switch to select which path from the available ones it will take

Instead, memory accesses are mediated by two internal components:

**IDU (Increment/Decrement Unit)** – computes next "addresses" of the selected address register

**Address Latch / Address Buffer** – exposes the address to the external bus

This means the CPU does not immediately access memory when the address source register changes.

The external memory address to use is selected **_only once per M-cycle_**, maybe at T1 (1st T-cycle of the M-Cycle).

The selected register becomes visible to memory only after being latched.

\[16-bit Register\] -> address_mux -> ADDRESS_LATCH -> external address bus

Something like this:
```
        +----+    (IDU Result Back)
        |    |<------------------------+
HL ---->|    |                         |
BC ---->| M  |                        IDU
DE ---->| U  |                         |
SP ---->| X  |----> ADDRESS BUS -------+----> [Address Buffer]
PC ---->|    |
WZ ---->|    |   (W and Z are temp 8-bit internal latches for immediate values)
        +----+
```

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