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100-days-of-RTL
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# 🚀 100 Days of RTL Challenge       Welcome to my **100 Days of RTL Challenge** repository! 🎉 In this project, I will be coding various digital designs using **Verilog** and **RTL** design techniques as part of a 100-day challenge to improve my hardware description language (HDL) skills. ## 📂 Repository Structure The repository is organized as follows: ``` ├── 100-days-of-RTL │ ├── day_xxx │ │ ├── src # Contains Verilog source files for the day's project │ │ ├── images # Visuals or screenshots of waveforms, RTL diagrams, etc. │ │ ├── <Project Folder> # Vivado project files for the design │ │ ├── <Day_XXX>.pdf # Documentation for the day's design │ ├── day_xxy │ ├── day_xyz │ ├── LICENSE # License file │ └── README.md # This readme file ``` Each day's folder includes all necessary files to reproduce the design. ### 🖥️ Vivado Projects Ready to Use I have uploaded complete Vivado project folders for each design. You can simply `clone` this repository and open these projects natively in  for simulation, synthesis, or further modifications. This ensures a seamless experience for anyone looking to explore or build upon my designs. ## 📅 Progress - **Day 1**: *Basic Gates using Behavioral Design* - **Day 2**: *Basic Gates using Structural Design* - **Day 3**: *Basic Gates using Gate Level Design* - **Day 4**: *MOS Inverter Design & Testbench* - **Day 5**: *Random Boolean Expression (ABC + A'C' + D)* - **Day 6**: *Half Adder & Full Adder* - **Day 7**: *Half Subtractor & Full Subtractor* - **Day 8**: *4-bit Parallel Adder with Control Input* - **Day 9**: *16-BIT ADDER AND SUBTRACTOR with Control input.* - **Day 10**: *Ripple Carry Adder using 4 Full Adders* - **Day 11**: *4-bit Binary Multiplier with Adder-Based Partial Product Summation* - **Day 12**: *Half Adder, Full Adder, Half Subtractor, Full Subtractor using Nand Gate* - **Day 13**: *BCD adder Using Verilog.* - **Day 14**: *4 Bit Divider* - **Day 15**: *4 Bit Magnitude Comparator* - **Day 16**: *Carry Look Ahead Generator* - **Day 17**: *Carry Select Adder* - **Day 18**: *Carry Save Adder* - **Day 19**: *Carry Skip Adder* - **Day 20**: *Even Parity Generator and Checker* - **Day 21**: *N bit Comparator* - **Day 22**: *Multiplexer [2:1]* - **Day 23**: *[4:1] Mux using [2:1]* - **Day 24**: *16x1 Mux using 2x1 Mux by instantiating in Verilog.* - **Day 25**: *K:1 Mux using parameter statement (K=64)* - **Day 26**: *Logic Gates using Mux* - **Day 27**: *Full Adder using Mux* - **Day 28**: *DeMultiplexer [1:2]* - **Day 29**: *DeMultiplexer[1:8] using [1:2]* - **Day 30**: *1:32 Demultiplexer Using Verilog.* - **Day 31**: *Logic Gates using Dmux* - **Day 32**: *1-Bit Comparator Using 4x1 Mux.* - **Day 33**: *Octal to binary Converter - Encoder [8:3]* - **Day 34**: *Priority Encoder* - **Day 35**: *Decoder [3:8]* - **Day 36**: *3x8 Decoder using 2x4 Decoder.* - **Day 37**: *5x32 Decoder using Verilog.* - **Day 38**: *BCD to Decimal Decoder* - **Day 39**: *watchdog timer (WDT)* - **Day 40**: *Monostable Multivibrator* - **Day 41**: *Input Majority Circuit [7 input]* - **Day 42**: *Binary to Gray code Converter* - **Day 43**: *Gray code to Binary Converter* - **Day 44**: *Binary to BCD Converter* - **Day 45**: *BCD to 7-Segment Converter* - **Day 46**: *SR Latch* - **Day 47**: *JK Flip Flop* - **Day 48**: *D Flip Flop* - **Day 49**: *T Flip Flop* - **Day 50**: *Arithmetic Logic Unit (ALU)* - **Day 51**: *SR flip flop using JK, D, T flip flops* - **Day 52**: *JK flip flop using SR, D, T flip flops* - **Day 53**: *D flip flop using SR, JK, T flip flops* - **Day 54**: *T flip flop using SR, JK, D flip flops* - **Day 55**: *Serial in Serial out (SISO) Register* - **Day 56**: *Serial in Parallel out (SIPO) Register* - **Day 57**: *Parallel in Serial out (PISO) Register* - **Day 58**: *Parallel in Parallel out (PIPO) Register* - **Day 59**: *Serial-in Serial-Out Shift Register Using JK Flip-Flop.* - **Day 60**: *Linear Feedback Shift Register (LFSR)* - **Day 61**: *Universal Shift Register* - **Day 62**: *Barrel Shifter* - **Day 63**: *Booth's Multiplication Algorithm* - **Day 64**: *Vedic Multiplier [4×4] using [2×2]* - **Day 65**: *Mod-N Counter* - **Day 66**: *Specific Sequence Counter* - **Day 67**: *Up/Down Counter* - **Day 68**: *Ring Counter* - **Day 69**: *Johnson Couter* - **Day 70**: *Clock Edge Detector* - **Day 71**: *Frequency Divider {even}* - **Day 72**: *Frequency Divider {odd}* - **Day 73**: *Frequency Divider {decimal}* - **Day 74**: *Two sequence detector using FSM* - **Day 75**: *16x16 Register File* - **Day 76**: *Cache Memory (Direct Mapping)* - **Day 77**: *Checking if Number is an Even or Odd Number* - **Day 78**: *Checking if Number is a Prime Number* - **Day 79**: *Checking if Number is a Pallindrome Number* - **Day 80**: *Checking if Number is an Armstrong Number* - **Day 81**: *Factorial of a Number* - **Day 82**: *Digital Clock* - **Day 83**: *Stopwatch* - **Day 84**: *One-HOT FSM* - **Day 85**: *Square Root and Cube Root of a Number* - **Day 86**: *Single Port RAM* - **Day 87**: *Dual Port RAM* - **Day 88**: *ROM [15* * *15]* - **Day 89**: *Synchronous FIFO(First In First Out)* - **Day 90**: *Synchronous LIFO(Last In First Out)* - **Day 91**: *Trafic Light Controller via FSM* - **Day 92**: *Washing Machine via FSM* - **Day 93**: *PWM (Pulse Width Modulation)* - **Day 94**: *Vending Machine* - **Day 95**: *Exponentiation Circuit* - **Day 96**: *Car Parking System* - **Day 97**: *Elevator Control System* - **Day 98**: *UART Protocol Demo* - **Day 99**: *Sine Wave Generator* - **Day 100**: *Synthesis and Implementation in FPGA (End-to-End Design) of a Binary to sevseg decoder* ## 🔧 Tools & Environment - **Vivado 2024.1** 🛠️ - The designs will be synthesized and simulated using the latest version of Xilinx Vivado (2024.1). ## 📜 License This project is licensed under the MIT License. See the [`LICENSE`](https://github.com/ItzzInfinity/100-days-of-RTL/tree/main?tab=MIT-1-ov-file) file for details. 
