FPGA-based-LSTM

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FPGA-based-LSTM

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A novel FPGA-based intent recognition systemutilizing deep recurrent neural networks

FPGA-based-LSTM 최신버젼 다운로드

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# FPGA-based-LSTM
A novel FPGA-based intent recognition system utilizing deep recurrent neural networks.

This repository contains the open-source C++ code of Vivado HLS/Vitis and the appropriate dataset for the FPGA acceleration of a RNN-LSTM model presented in the following paper:

Zhang, X.; Yao, L.; Huang, C.; Sheng, Q.; Wang, X. Intent recognition in smart living through deep recurrent neural networks.24th International Conference on Neural Information Processing (ICONIP 2017) : proceedings; Liu, D.; Zhao, D.; Xie, S.; El-Alfy,E.;  Li, Y., Eds.;  Springer, Springer Nature:  United States, 2017;  Vol.  10635,Lecture Notes in Computer Science, pp.  748–758.doi:10.1007/978-3-319-70096-0_76.

The folder "dataset" contains all the weights and biases in .csv files of the trained model that will be used as inputs to the FPGA implementation. Moreover, the testing data and the results produced by the original Python code duting training are included.

The "rnn_model_tb.cpp", "rnn_model.cpp" and "rnn_LSTM.cpp" contain the three source code of the FPGA implementation in Vivado HLS/Vitis. 
The first one presents the testbench which imports the .csv files into simple tables and calls for the execution of the optimized FPGA-based model.
The last two are the complete optimazed FPGA-based model which achieves excellent accelaration and energy efficiency. Specifically, the "rnn_LSTM.cpp" contains the optimized LSTM layers of the model and the "rnn_model.cpp" the rest of the layers.

In order to reproduce the same results as the corresponding paper, the following steps must be performed:
1. For each .cpp file create a seperate file in Vivado HLS/Vitis and copy its contends in the Vivado HLS/Vitis files. The "rnn_model_tb.cpp" contains the testbench therefore must be included in the appropriate testbench of the project.
2. Download and save in a accessable place the "dataset" folder. Afterwards, in the testbench file edit the present address of the folder in all previous addresses. Therefore, the model can import the correct inputs and produce the propriate results.
3. The model is ready to be tested in Vivado HLS/Vitis.

FPGA-based-LSTM

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