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HLS IP Gen Code Samples

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# HLS Samples for Field Programmable Gate Arrays (FPGAs)

The hls-samples GitHub repository include tutorials, reference designs, and libraries specific to field programmable gate array (FPGA) features of the HLS IP Gen Compiler.

You will need the following toolkit:

- HLS IP Gen Compiler.

>**Note**: This repository is specific to versions of the HLS IP Gen Compiler. For use with earlier versions of the Intel® oneAPI toolkit, one should use the [oneapi-src/oneAPI-samples](https://github.com/oneapi-src/oneAPI-samples/tree/main/DirectProgramming/C%2B%2BSYCL_FPGA) repository.
Use the latest [release version](https://github.com/altera-fpga/hls-samples/tags) of the repository that corresponds to the version of the compiler you are using.

## Get the HLS Samples

Clone the repository by entering the following command:

`git clone https://github.com/altera-fpga/hls-samples.git`

Alternatively, you can download a zip file containing the primary branch in repository.

1. Click the **Code** button.
2. Select **Download ZIP** from the menu options.
3. After downloading the file, unzip the repository contents.

### Understand FPGA Programming

The section [Introduction To FPGA Design Concepts](https://docs.altera.com/r/docs/m615048/current/hls-ip-gen-handbook/3-introduction-to-fpga-design-concepts) contains information on the basic concepts that are foundational to FPGA programming. Read that section to get the most from these FPGA samples.

## FPGA Repository Structure

This area of the hls-samples repository has a general structure intended to help you find the resources.

- [Tutorials](Tutorials)
  - [GettingStarted](Tutorials/GettingStarted): Contains basic samples to get you through your first compiles.
  - [Features](Tutorials/Features): Contains samples that demonstrate useful compiler features, like loop unrolling.
  - [DesignPatterns](Tutorials/DesignPatterns): Contains samples that show coding patterns to generate efficient hardware usage.
  - [Tools](Tutorials/Tools): Contains sample to demonstrate how to use Platform Designer with your IP core.
- [ReferenceDesigns](ReferenceDesigns): Contains samples that showcase high-performance designs that take advantage of multiple features and design patterns shown in the *Tutorials* section.
- [include](include): Contains commonly used functions wrapped as libraries.

### Sample Categories

To help you understand and use the code samples in a coherent manner, the samples are categorized by the tiers.

- [Tier 1](#tier-1-get-started): Get Started
- [Tier 2](#tier-2-explore-the-fundamentals): Explore the Fundamentals
- [Tier 3](#tier-3-explore-the-advances-techniques): Explore the Advanced Techniques
- [Tier 4](#tier-4-explore-the-reference-designs): Explore the Reference Designs

#### Tier 1: Get Started

```mermaid
flowchart LR
   tier1("Tier 1: Get Started")
   tier2("Tier 2: Explore the Fundamentals")
   tier3("Tier 3: Explore the Advanced Techniques")
   tier4("Tier 4: Explore the Reference Designs")
   
   tier1 --> tier2 --> tier3 --> tier4
   
   style tier1 fill:#f96,stroke:#333,stroke-width:1px,color:#fff
   style tier2 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
   style tier3 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
   style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
```

| Sample | Category | Description
|:--- |:--- |:---
| [fpga_compile](Tutorials/GettingStarted/fpga_compile) | [Tutorials/GettingStarted](Tutorials/GettingStarted) | How and why compiling SYCL* code for FPGA differs from CPU or GPU FPGA device image types and when to use them. The compile options used to target FPGA
| [fast_recompile](Tutorials/GettingStarted/fast_recompile) | [Tutorials/GettingStarted](Tutorials/GettingStarted) | Why to separate host and device code compilation in your FPGA project How to use the `-reuse-exe` and device link. Which method to choose for your project
| [fpga_template](Tutorials/GettingStarted/fpga_template) | [Tutorials/GettingStarted](Tutorials/GettingStarted) | An FPGA tutorial that explains the CMake build system that is used in other code samples, and serves as a template that you can re-use in your own designs
| [component_interfaces_comparison](Tutorials/Features/hls_flow_interfaces/component_interfaces_comparison) | [Tutorials/Features/hls_flow_interfaces](Tutorials/Features/hls_flow_interfaces) | This sample introduces different invocation/data interfaces that can be used for IP components
| [platform_designer](Tutorials/Tools/platform_designer) | [Tutorials/Tools](Tutorials/Tools) | How to use FPGA IP produced with the HLS IP Gen Compiler with Quartus® Prime Pro Edition software suite and Platform Designer
| [platform_designer_standard](Tutorials/Tools/platform_designer_standard) | [Tutorials/Tools](Tutorials/Tools) | How to use FPGA IP produced with the HLS IP Gen Compiler with Quartus® Prime Standard Edition software suite and Platform Designer

#### Tier 2: Explore the Fundamentals

```mermaid
flowchart LR
   tier1("Tier 1: Get Started")
   tier2("Tier 2: Explore the Fundamentals")
   tier3("Tier 3: Explore the Advanced Techniques")
   tier4("Tier 4: Explore the Reference Designs")
   
   tier1 --> tier2 --> tier3 --> tier4
   
   style tier1 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
   style tier2 fill:#f96,stroke:#333,stroke-width:1px,color:#fff
   style tier3 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
   style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
```

| Sample | Category | Description
|:--- |:--- |:---
| [ac_fixed](Tutorials/Features/ac_fixed) | [Tutorials/Features](Tutorials/Features) | How different methods of `ac_fixed` number construction affect hardware resource utilization Recommended method for constructing `ac_fixed` numbers in your kernel Accessing and using the `ac_fixed` math library functions Trading off accuracy of results for reduced resource usage on the FPGA
| [ac_int](Tutorials/Features/ac_int) | [Tutorials/Features](Tutorials/Features) | Using the `ac_int` data type for basic operations Efficiently using the left shift operation Setting and reading certain bits of an `ac_int` number
| [device_global (experimental)](Tutorials/Features/experimental/device_global) | [Tutorials/Features](Tutorials/Features) | The basic usage of the `device_global` class How to initialize a `device_global` to non-zero values
| [explicit_data_movement](Tutorials/DesignPatterns/explicit_data_movement) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How to explicitly manage the movement of data for the FPGA
| [hardware_reuse](Tutorials/Features/task_sequence/hardware_reuse) | [Tutorials/Features](Tutorials/Features) | How to reuse hardware in your FPGA designs by using loops and task sequences
| [hostpipes (experimental)](Tutorials/Features/experimental/hostpipes) | [Tutorials/Features](Tutorials/Features) | How to use host pipes to send and receive data between a host and the FPGA 
| [invocation_interfaces](Tutorials/Features/hls_flow_interfaces/invocation_interfaces) | [Tutorials/Features/hls_flow_interfaces](Tutorials/Features/hls_flow_interfaces) | How to specify the kernel invocation interface and kernel argument interfaces
| [kernel_args_restrict](Tutorials/Features/kernel_args_restrict) | [Tutorials/Features](Tutorials/Features) | The problem of pointer aliasing and its impact on compiler optimizations. The behavior of the `kernel_args_restrict` attribute and when to use it on your kernel The effect this attribute can have on kernel performance on FPGA
| [loop_coalesce](Tutorials/Features/loop_coalesce) | [Tutorials/Features](Tutorials/Features) | What the `loop_coalesce` attribute does How `loop_coalesce` attribute affects resource usage and loop throughput How to apply the `loop_coalesce` attribute to loops in your program Which loops make good candidates for coalescing
| [loop_fusion](Tutorials/Features/loop_fusion) | [Tutorials/Features](Tutorials/Features) | Basics of loop fusion The reasons for loop fusion How to use loop fusion to increase performance Understanding safe application of loop fusion
| [loop_initiation_interval](Tutorials/Features/loop_initiation_interval) | [Tutorials/Features](Tutorials/Features) | The fMAX-II tradeoff Default behavior of the compiler when scheduling loops How to use `intel::initiation_interval` to attempt to set the II for a loop Scenarios in which `intel::initiation_interval` can be helpful in optimizing kernel performance
| [loop_ivdep](Tutorials/Features/loop_ivdep) | [Tutorials/Features](Tutorials/Features) | Basics of loop-carried dependencies The notion of a loop-carried dependence distance What constitutes a safe dependence distance How to aid the compiler's dependence analysis to maximize performance
| [loop_unroll](Tutorials/Features/loop_unroll) | [Tutorials/Features](Tutorials/Features) | Basics of loop unrolling. How to unroll loops in your program Determining the optimal unroll factor for your program
| [max_interleaving](Tutorials/Features/max_interleaving) | [Tutorials/Features](Tutorials/Features) | The basic usage of the `max_interleaving` attribute How the `max_interleaving` attribute affects loop resource use How to apply the `max_interleaving` attribute to loops in your program
| [memory_attributes](Tutorials/Features/memory_attributes) | [Tutorials/Features](Tutorials/Features) | The basic concepts of on-chip memory attributes How to apply memory attributes in your program How to confirm that the memory attributes were respected by the compiler A case study of the type of performance/area trade-offs enabled by memory attributes
| [mmhost](Tutorials/Features/hls_flow_interfaces/mmhost) | [Tutorials/Features/hls_flow_interfaces](Tutorials/Features/hls_flow_interfaces) | Basics of declaring Avalon memory-mapped host data interfaces for IP components
| [parallel_loops](Tutorials/Features/task_sequence/parallel_loops) | [Tutorials/Features](Tutorials/Features) | How to use task sequences to describe multiple parallel loops in a single kernel
| [pipes](Tutorials/Features/pipes) | [Tutorials/Features](Tutorials/Features) | The basics of using SYCL*-compliant pipes extension for FPGA How to declare and use pipes
| [printf](Tutorials/Features/printf) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How to declare and use `printf` in program
| [streaming_data_interfaces](Tutorials/Features/hls_flow_interfaces/streaming_data_interfaces) | [Tutorials/Features/hls_flow_interfaces](Tutorials/Features/hls_flow_interfaces) | How to use pipes to implement streaming data interfaces on an IP component

#### Tier 3: Explore the Advanced Techniques

```mermaid
flowchart LR
   tier1("Tier 1: Get Started")
   tier2("Tier 2: Explore the Fundamentals")
   tier3("Tier 3: Explore the Advanced Techniques")
   tier4("Tier 4: Explore the Reference Designs")
   
   tier1 --> tier2 --> tier3 --> tier4
   
   style tier1 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
   style tier2 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
   style tier3 fill:#f96,stroke:#333,stroke-width:1px,color:#fff
   style tier4 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
```

| Sample | Category | Description
|:--- |:--- |:---
| [annotated_class_clean_coding (experimental)](Tutorials/Features/experimental/annotated_class_clean_coding) | [Tutorials/Features](Tutorials/Features) | How to use `annotated_class_util.hpp` to simplify your SYCL code that annotates properties to `pipe`s and `annotated_arg`
| [annotated_ptr (experimental)](Tutorials/Features/experimental/annotated_ptr) | [Tutorials/Features](Tutorials/Features) | How to use `annotated_ptr` to constrain a specific memory access
| [autorun](Tutorials/DesignPatterns/autorun) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How and when to use autorun kernels
| [banked_memory_system](Tutorials/DesignPatterns/banked_memory_system) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How to optimize a banked memory system and improve throughput
| [compute_units](Tutorials/DesignPatterns/compute_units) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | A design pattern to generate multiple compute units using template metaprogramming
| [dsp_control](Tutorials/Features/dsp_control) | [Tutorials/Features](Tutorials/Features) | How to apply global DSP control in command-line interface How to apply local DSP control in source code Scope of datatypes and math operations that support DSP control
| [fpga_reg](Tutorials/Features/fpga_reg) | [Tutorials/Features](Tutorials/Features) | How to use the `ext::altera::fpga_reg` extension How `ext::altera::fpga_reg` can be used to re-structure the compiler-generated hardware Situations in which applying `ext::altera::fpga_reg` might be beneficial
| [latency_control (experimental)](Tutorials/Features/experimental/latency_control) | [Tutorials/Features](Tutorials/Features) | How to set latency constraints to pipes and LSUs accesses How to confirm that the compiler respected the latency control directive
| [loop_carried_dependency](Tutorials/DesignPatterns/loop_carried_dependency) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | A technique to remove loop carried dependencies from your FPGA device code, and when to apply it
| [lsu_control](Tutorials/Features/lsu_control) | [Tutorials/Features](Tutorials/Features) | The basic concepts of LSU styles and LSU modifiers How to use the LSU controls extension to request specific configurations How to confirm what LSU configurations are implemented A case study of the type of area trade-offs enabled by LSU
| [max_reinvocation_delay](Tutorials/Features/max_reinvocation_delay) | [Tutorials/Features](Tutorials/Features) | How and when to apply the `max_reinvocation_delay` attribute when optimizing loop throughput
| [onchip_memory_cache](Tutorials/DesignPatterns/onchip_memory_cache) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How and when to implement the on-chip memory cache optimization
| [optimization_targets](Tutorials/Features/optimization_targets) | [Tutorials/Features](Tutorials/Features) | How to set optimization targets for your compileHow to use the minimum latency optimization target to compile low-latency designs How to manually override underlying controls set by the minimum latency optimization target
| [optimize_inner_loop](Tutorials/DesignPatterns/optimize_inner_loop) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How to optimize the throughput of an inner loop with a low trip
| [pipe_array](Tutorials/DesignPatterns/pipe_array) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | A design pattern to generate an array of pipes using SYCL* Static loop unrolling through template metaprogramming
| [private_copies](Tutorials/Features/private_copies) | [Tutorials/Features](Tutorials/Features) | The basic usage of the `private_copies` attribute How the `private_copies` attribute affects the throughput and resource use of your FPGA program How to apply the `private_copies` attribute to variables or arrays in your program How to identify the correct `private_copies` factor for your program
| [read_only_cache](Tutorials/Features/read_only_cache) | [Tutorials/Features](Tutorials/Features) | How and when to use the read-only cache feature
| [restartable_streaming_kernel](Tutorials/DesignPatterns/restartable_streaming_kernel) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How to make a restartable kernel. The technique shown in this tutorial lets you dynamically terminate your kernel while it runs, allowing it to load a new set of kernel arguments.
| [scheduler_target_fmax](Tutorials/Features/scheduler_target_fmax) | [Tutorials/Features](Tutorials/Features) | The behavior of the `scheduler_target_fmax_mhz` attribute and when to use it The effect this attribute can have on kernel performance on FPGA
| [shannonization](Tutorials/DesignPatterns/shannonization) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How to make FPGA-specific optimizations to remove computation from the critical path and improve fMAX/II
| [speculated_iterations](Tutorials/Features/speculated_iterations) | [Tutorials/Features](Tutorials/Features) | What the `speculated_iterations` attribute does How to apply the `speculated_iterations` attribute to loops in your program How to determine the optimal number of speculated iterations
| [stall_enable](Tutorials/Features/stall_enable) | [Tutorials/Features](Tutorials/Features) | What the `use_stall_enable_clusters` attribute does How `use_stall_enable_clusters` attribute affects resource usage and latency How to apply the `use_stall_enable_clusters` attribute to kernels in your program
| [triangular_loop](Tutorials/DesignPatterns/triangular_loop) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How and when to apply the triangular loop optimization technique
| [use_library](Tutorials/Tools/use_library) | [Tutorials/Tools](Tutorials/Tools) | How to integrate Verilog RTL into your SYCL design directly
| [zero_copy_data_transfer](Tutorials/DesignPatterns/zero_copy_data_transfer) | [Tutorials/DesignPatterns](Tutorials/DesignPatterns) | How to use SYCL USM host allocations for the FPGA

#### Tier 4: Explore the Reference Designs

```mermaid
flowchart LR
   tier1("Tier 1: Get Started")
   tier2("Tier 2: Explore the Fundamentals")
   tier3("Tier 3: Explore the Advanced Techniques")
   tier4("Tier 4: Explore the Reference Designs")
   
   tier1 --> tier2 --> tier3 --> tier4
   
   style tier1 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
   style tier2 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
   style tier3 fill:#0071c1,stroke:#0071c1,stroke-width:1px,color:#fff
   style tier4 fill:#f96,stroke:#333,stroke-width:1px,color:#fff
```

All the Tier 4 samples are in the [ReferenceDesigns](ReferenceDesigns) category.

| Sample                                                    | Description
|:---                                                       |:---
| [anr](ReferenceDesigns/anr)                               | How to create a parameterizable image processing pipeline to implement an Adaptive Noise Reduction (ANR) algorithm on a FPGA
| [cholesky](ReferenceDesigns/cholesky)                     | How to implement high performance matrix Cholesky decomposition on a FPGA
| [cholesky_inversion](ReferenceDesigns/cholesky_inversion) | How to implement high performance Cholesky matrix decomposition on a FPGA
| [convolution_2d](ReferenceDesigns/convolution2d)          | How to implement a 2D convolution IP component that can be exported to Quartus® Prime
| [crr](ReferenceDesigns/crr)                               | How to implement the Cox-Ross-Rubinstein (CRR) binomial tree model on a FPGA
| [db](ReferenceDesigns/db)                                 | How to accelerate database queries using an FPGA
| [decompress](ReferenceDesigns/decompress)                 | How to implement an efficient GZIP and Snappy decompression engine on a FPGA
| [fft2d](ReferenceDesigns/fft2d)                           | How to implement an efficient 2D FFT on a FPGA
| [gzip](ReferenceDesigns/gzip)                             | How to implement a high-performance multi-engine compression algorithm on FPGA
| [matmul](ReferenceDesigns/matmul)                         | How to implement a systolic-array-based high-performance matrix multiplication algorithm on FPGA
| [merge_sort](ReferenceDesigns/merge_sort)                 | How to use the spatial compute of the FPGA to create a merge sort design that takes advantage of thread- and SIMD-level parallelism
| [mvdr_beamforming](ReferenceDesigns/mvdr_beamforming)     | How to create a full, complex system that performs IO streaming using SYCL*-compliant code
| [niosv](ReferenceDesigns/niosv/)                          | Simulate a system with an FPGA IP produced with the HLS IP Gen Compiler, and a Nios® V softcore processor.
| [pca](ReferenceDesigns/pca)                               | How to implement high performance principal component analysis on a FPGA
| [qrd](ReferenceDesigns/qrd)                               | Implementing a high performance FPGA version of the Gram-Schmidt QR decomposition algorithm
| [qri](ReferenceDesigns/qri)                               | Implementing a high performance FPGA version of the Gram-Schmidt QR decomposition to compute a matrix inversion
| [svd](ReferenceDesigns/svd)                               | How to implement a high performance Singular Value Decomposition on an FPGA

#### Start exploring the FPGA code samples with this selection

The following FPGA samples represent a selection of useful tutorials suitable to get you started on your first SYCL application on the FPGA

## Build and Run the Samples on Local Development System

Each sample contains a `README.md` file with instructions to build and run the sample. The following sections contain information about configuring your development environment to build and run the samples; in most cases, the sample `README.md` file contains specific instructions.

### Set Environment Variables

When working with the command-line interface (CLI), you should configure the HLS IP Gen Compiler using environment variables.
Set up your CLI environment by sourcing the `fpgavars` script every time you open a new terminal window.
This practice ensures that your compiler, libraries, and tools are ready for development.
>
> Linux*:
> - `source <install-dir>/fpgavars.sh`
> - For non-POSIX shells, like csh, use the following command: `bash -c 'source <install-dir>/fpgavars.sh ; exec csh'`

### Include Files

The FPGA samples use many of the headers in the [`include`](include) folder.

### Troubleshooting

If an error occurs when compiling a sample, you can get more details by running `make` with the `VERBOSE=1` argument:
``make VERBOSE=1``

## Performance Disclaimers

Tests document performance of components on a particular test, in specific systems and may not reflect all publicly available security updates. 
Differences in hardware, software, or configuration will affect actual performance. 
Consult other sources of information to evaluate performance as you consider your purchase. 
For complete information about performance and benchmark results, visit [this page](https://edc.intel.com/content/www/us/en/products/performance/benchmarks/overview).
See configuration disclosure for details.
No product or component can be absolutely secure.

## Documentation

- The [Altera® HLS IP Gen Handbook](https://docs.altera.com/r/docs/m615048/current) helps you understand how to use the Altera HLS IP Gen compiler.
- The [Altera® HLS IP Gen Compiler Release Notes](https://docs.altera.com/r/docs/m707363/current/hls-ip-gen-release-notes/preface).
- The [Migrating OpenCL™ FPGA Designs to SYCL*](https://docs.altera.com/r/docs/767849/2024/migrating-opencltm-fpga-designs-to-sycl/download-document) guide.
- The [Quartus® Prime Pro and Standard Software User Guides](https://www.altera.com/design/guidance/software/quartus-user-guides).

## Licenses

The HLS Samples are licensed under the MIT license. See [License.txt](/License.txt) for details.

Third-party program licenses can be found here: [third-party-programs.txt](/third-party-programs.txt).

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