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riscv32i-cpu-chisel
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riscv32i-cpu
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riscv32i-cpu-chisel
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Tsinghua University Computer Systems Organization ================================================= [](https://github.com/riscv-and-rust-and-decaf/riscv32i-cpu-chisel/actions) This is the CPU part of the course project for the CSO course in Tsinghua University. The main objective is to code a CPU implementing at least RV32I with transparent TLB, using the Chisel hardware control language. LICENSE ======= Licensed under the *glorious people's license*: GPL v3.0.
