30-days-of-verilog

KO | EN

gitlite — search

#javascript #python #hacktoberfest #react #ai #golang #rust #docker #macos #kubernetes #awesome-list #vue #security #openai

30-days-of-verilog

(★ 73)

30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!

30-days-of-verilog 최신버젼 다운로드

최종 버전 다운로드 (.zip)

// repository documentation

Was this content helpful?

★ 0 (0 ratings)

# 30 Days of Verilog

### Repo was not updated daily. I posted consistently on Linkedin

<p align="center">
  Embark on a journey through 30 days of Verilog exploration! 🌟
</p>

Welcome to my personal project: **30 Days of Verilog**. Over the next 30 days, I'll be taking a deep dive into the world of digital circuits and Verilog programming. My goal is to create and showcase 30 different digital circuits, each implemented using Verilog HDL.

## About the Project

The aim of this project is to:

- **Learn Verilog**: Gain a solid understanding of Verilog and its applications.
- **Explore Digital Circuits**: Create a variety of digital circuits to explore different concepts.
- **Document Progress**: Document my journey, challenges, and solutions for each circuit.
- **Share with the Community**: Provide a resource for others interested in Verilog and digital design.

## Repository Structure

Each day, I will add a new folder from **Day 1** to **Day 30**, containing:

- **Verilog Code**: Implementation of the day's digital circuit in Verilog.
- **README**: Explanation of the circuit, its purpose, and my approach.
- **Simulation**: Simulation results, waveforms, and test benches (if applicable).
- **Reflections**: Insights and lessons learned during the implementation.

Feel free to follow along, offer suggestions, or learn from my progress!

## Table of Contents

- [Day 1: Half Adder & Full Adder](./Day1)
- [Day 2: Ripple Carry Adder](./Day2)
- [Day 3: Code Conversion(Gray & Binary)](./Day3)
- [Day 4: Multiplexers](./Day4)
- [Day 5: Demultiplexers](./Day5)
- [Day 6: Encoders](./Day6)
- [Day 7: Decoders](./Day7)
- [Day 8: Latches](./Day8)
- [Day 9: Flip-flops](./Day9)
- [Day 10: Comparators](./Day_10)
- [Day 11: Shift Registers (1)](./Day_11)
- [Day 12: Shift Registers (2)](./Day_12)
- [Day 13: Counters](./Day_13)
- [Day 14: MOD-N Counter](./Day_14)
- [Day 15: Gray Counter](./Day_15)
- [Day 16: Booth Multiplier](./Day_16)
- [Day 17: 1-bit RAM cell](./Day_17)
- [Day 18: 4-Bit & 8-Bit RAM](./Day_18)
- [Day 19: 1,4,8-Bit ROM](./Day_19)
- [Day 20: 8-Bit ALU](./Day_20)
- [Day 21: 1101 Moore Sequence Detector](./Day_21)
- [Day 22: 1010 Mealy Sequence Detector](./Day_22)
- [Day 23: PWM (Pulse Width Modulation) generator](./Day_23)
- [Day 24: Fixed Priority Arbiter](./Day_24)
- [Day 25: Round-Robin Arbiter](./Day_25)
- [Day 26: Pseudorandom number generator](./Day_26)
- [Day 27: Frequency Divider by Even Numbers](./Day_27)
- [Day 28: Traffic Light Controller](./Day_28)
- [Day 29: Elevator Controller](./Day_29)
- [Day 30: Factorial](./Day_30)

## Let's Connect

I'd love to share my journey with you and connect with fellow Verilog enthusiasts:

- Follow me on [GitHub](https://github.com/akashtailor-exe) to stay updated.
- Connect on [LinkedIn](https://www.linkedin.com/in/akash-tailor) for more discussions.
- Reach out via email at [tailorakash2320@gmail.com](mailto:tailorakash2320@gmail.com).

## Stay Tuned

Join me as I explore the world of Verilog programming and digital circuits over the next 30 days. Let's explore, create, and learn together!

<p align="center">
  Happy Verilog coding! 💻
</p>

30-days-of-verilog

30-days-of-verilog 최신버젼 다운로드

오늘의 추천 프로젝트

Was this content helpful?

Recent Feedback

30-days-of-verilog

30-days-of-verilog 최신버젼 다운로드

오늘의 추천 프로젝트

Was this content helpful?

Recent Feedback

Download README