RTL_Design_and_Synthesis_Workshop_Using_SKY130

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RTL_Design_and_Synthesis_Workshop_Using_SKY130

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# RTL_Design_and_Synthesis_Workshop_Using_SKY130

The agenda of this workshop is to understand the RTL Design and Synthesis process in VLSI using various open-source tools. This process is where we provide the synthesis netlist to the Physical Design team. By the end of this workshop, we will be able to understand how logic conversion takes place from a simple verilog code written for any level of logic.

## DAY 1: Introduction to Verilog RTL design and Synthesis
    L1 - Learn about open-source simulator "iverilog"
    L2 - Start with Yosys and Sky130 PDKs

## DAY 2: Timing libs, hierarchical vs flat synthesis and efficient flop coding styles
    L1 - Understanding timing .libs
    L2 - Hierarchical vs Flat Synthesis
    L3 - Various Flop Coding Styles and Optimization

## DAY 3: Combinational and sequential optimizations
    L1 - Introduction to optimizations
    L2 - Combinational logic optimizations
    L3 - Sequential logic optimizations
    L4 - Sequential optimizations for unused outputs

## DAY 4: GLS blocking vs non-blocking and Synthesis-Simulation mismatch
    L1 - GLS blocking vs non-blocking and Synthesis-Simulation mismatch statements

## DAY 5: Optimization in synthesis
    L1 - If Case constructs
    L2 - For loop and for generate

## Workshop details are recorded separately in THEORY and LAB SESSION files below

--> [THEORY_SESSIONS](THEORY_SESSIONS.md)

--> [LAB_SESSIONS](LAB_SESSIONS.md)

RTL_Design_and_Synthesis_Workshop_Using_SKY130

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