iclr-circuitnet_3.0

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iclr-circuitnet_3.0

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# CircuitNet 3.0

Public code release for the ICLR 2026 paper [CircuitNet 3.0: A Multi-Modal Dataset with Task-Oriented Augmentation for AI-Driven Circuit Design](https://openreview.net/forum?id=lEDb4gQ4dB).

This repository is the public code and lightweight-metadata companion to the dataset release. It keeps the reproducible, shareable parts of the rebuttal-time repository and leaves the large data assets on Hugging Face.

## What this repository contains

- [RTL_ast_mutator_function_different.py](RTL_ast_mutator_function_different.py): AST-based Verilog mutation utilities
- [RTLclassificationbyLLM.py](RTLclassificationbyLLM.py): LLM-based RTL categorization and report generation
- [original_RTL_classification_results/](original_RTL_classification_results/): final classification statistics and detailed CSV outputs
- [dataset_circuit_analysis_visualization/](dataset_circuit_analysis_visualization/): lightweight analysis plots used in the paper and rebuttal
- [github_v_tb_description.jsonl](github_v_tb_description.jsonl) and [opencore_v_tb_description.jsonl](opencore_v_tb_description.jsonl): compact RTL/testbench description metadata

## What is intentionally excluded

- Commercial PDK files, standard-cell libraries, and other restricted technology collateral
- Proprietary EDA binaries or license-dependent artifacts
- Large layout, netlist, and generated design collections that are better hosted as dataset artifacts
- Redundant internal examples that do not improve reproducibility

## Public data release

The canonical dataset distribution is hosted on Hugging Face:
[SKLP-EDA-LAB/CircuitNet3.0](https://huggingface.co/datasets/SKLP-EDA-LAB/CircuitNet3.0)

The Hugging Face release is updated incrementally. Large layout artifacts are uploaded in batches or shared on request, because they are too large to mirror directly in the code repository. If you need a specific layout subset or cannot find a file you expect, please contact [wangmingjun000613@gmail.com](mailto:wangmingjun000613@gmail.com).

## Dataset summary

- 8,659 validated open-source RTL designs
- 15,863 total design instances after task-oriented augmentation
- Source-level train/validation/test partitioning, with augmented variants of test sources excluded from train/val to avoid leakage
- Modalities and labels covering RTL, synthesized netlists, layout-related artifacts, timing, and power

## Repository role

- GitHub: code, scripts, documentation, and lightweight metadata
- Hugging Face: dataset hosting, incremental updates, and large artifacts

## Paper

This repository accompanies the paper:
[CircuitNet 3.0: A Multi-Modal Dataset with Task-Oriented Augmentation for AI-Driven Circuit Design](https://openreview.net/forum?id=lEDb4gQ4dB)

If you use the code or data, please cite the paper above.

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