mmRISC-1

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RISC-V RV32IMAFC Core for MCU

mmRISC-1 최신버젼 다운로드

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# mmRISC-1 : RISC-V RV32IMAFC Core for MCU

“mmRISC_1” is a RISC-V compliant CPU core with RV32IM[A][F]C ISA for MCU. 
The “mmRISC” stands for “much more RISC”. 
For details, please refer PDF file under doc directory.

## Technical Notes

### 2026.05.21 Following update is applied. 
There was an issue where debuggers using the cJTAG interface in certain commercial integrated development environments (IDEs) failed to connect to the cJTAG interface of the mmRISC-1. 
This occurred because the initial waveforms (online/activation) during the commercial IDE's cJTAG connection sequence are designed to trigger a connection error first, requiring a recovery process in the CPU core's RTL logic that was previously insufficient. 
This issue has been resolved by updating the RTL logic in "cjtag_2_jtag.v".

### 2025.02.01 Following update is applied. 
Updated the document "mmRISC-1 Technical Reference Manual" to Rev07. In the section of "Connection to the target FPGA as 2-wire cJTAG interface", added a figure to show the connection between the cJTAG debugger probe and the cJTAG signals. 
No technology files are modified such as RTLs.

### 2025.01.26 Following updates are applied. 
(1) The address expression for the TINFO Register (CSR) of the Debug Trigger Module has been corrected from 0x7a3 to 0x7a4 in the document. This error was only present in the document and did not aﬀect the RTL logic. 
(2) The cause field in the DCSR Register (CSR) of the Debug related function was previously set to 3’b011 (halt request) even when the cause was a Hardware Break Point. This has been corrected in the RTL description to 3’b010 (breakpoint exception by hardware trigger module) when the cause is a Hardware Break Point. The corrected RTL file is cpu_pipeline.v. This cause field is used by some commercial IDEs to implement specific I/O emulation, such as printf().

### 2024.09.01 Following updates are applied. 
(1) You can switch the debug interface between 4-wire JTAG or 2-wire cJTAG by setting the signal level of "enable_cjtag" in chip\_top\_wrap.v. This signal is connected to GPIO2[6] corresponding to SW6 on DE10-Lite board. Therefore from this version onward, there are only two FPGA conﬁgurations; one is RV32IMAFC_JTAGcJTAG, which uniﬁes previous RV32IMAFC_JTAG and RV32IMAFC\_cJTAG; the other is RV32IMAC\_JTAGcJTAG, which uniﬁes previous RV32IMAC\_JTAG and RV32IMAFC\_cJTAG. 
(2) Even in the previous version, the detection of escape sequences in "cJTAG_2\_JTAG.v" operated correctly for cJTAG waves generated by OpenOCD. However, the logic could not correctly detect some cJTAG escape waves generated by other generic debuggers, such as commercial RISC-V development IDEs. Additionally, in "debug\_dtm\_jtag.v", the IR in the JTAG TAP controller set to 0x1F caused the TDO output to be ﬁxed high, which led to failures in JTAG chain tests when shifting long bit chains. These bugs have been ﬁxed in this version, and now the mmRISC-1 can connect to generic commercial IDEs correctly. 
(3) Fixed a bug in the pipeline stall control for the C.FSWSP instruction (RV32FC). In the previous version, if the destination of the previous instruction was FRn, and the C.FSWSP stored the same FRn, the C.FSWSP did not stall correctly. 
(4) In the sample application programs, the interrupt handler routines have been re-written using "\_\_attribute\_\_ ((interrupt))", and the control of interrupt nesting has been moved to the C routine "interrupt.c" from the assembler routine "startup.S". 
(5) Updated the document "mmRISC-1\_TRM.pdf" to refletct the above changes.

### 2023.11.20 Following updates are applied. 
(1) Added cJTAG (2-wire compact JTAG) as the debug interface. You can select the debug interface from JTAG or cJTAG. 
(2) Added alternative Halt-On-Reset, controlled by a hardware input signal level, instead of the one in standard RISC-V debug function. 
(3) Added a new JTAG DR register for user’s multi purposes, for example, to configure the operation modes of the SoC from JTAG/cJTAG interface. 
(4) The number of 32bit secure code for authentication is expanded from one to two. 
(5) Supported low power mode (STBY). 
(6) Added precise verification methods for floating point operations. Corrected RTL code in conversion from float to int (cpu_fpu32.v). 
(7) Added a application program; Tic-Tac-Toe AI Game on Touch LCD panel. 
(8) Fixed a bug in priority tournament logic in interrupt controller (cpu_csr_int.v).

### 2022.05.04 Repaired directory contentes in riscv-arch-test and riscv-tests
Some files and directories were lacked in riscv-arch-test and riscv-tests. Repaired them.

### 2022.05.03 Corrected Test Banch Codes
(1) In simulation/modelsim/mmRISC_Simulation, simulation/modelsim/riscv-tests and simulation/modelsim/riscv-arch-test, corrected test banch top RTL (tb_TOP.v) and simulation script (sim_TOP.do) in each directory. 
(2) Correct minor typo in comment of uart.v. 
(3) Body RTL codes of mmRISC and its SOC(FPGA) do not have any bugs.

### 2022.05.01 Added Simple SPI, one more I2C in FPGA. Added an application mmRISC_TouchLCD
(1) Added SPI, one more I2C. 
(2) Wrote know-hows in Technical Reference Manual to use Raspberry Pi as a Development Environment including OpenOCD interface. Added an example of openocd script for Raspberry Pi in directory "openocd". 
(3) In application mmRISC_SampleCPU, added access of Acceleration Sensor on MAX10-Lite board through I2C interface. 
(4) Added new application mmRISC_TouchLCD which handles Adafruit-2-8-tft-touch-shield-v2 with Resistive Touch Panel or Capacitive Touch Panel for Arduino. 
(5) In each sample program, baud rate of UART is unified to 115200bps.

### 2022.05.01 Fixed Operation of RV32F Instruction in which source registers are FRn and destination register is XRn. 
 BUG : When RV32F Instruction in which destination register is XRn, such as FMV.X.W, FCLASS.S, FCMP,FCVT.W(U).S and FCMP.S, is followed by an instruction in which above XRn is used as source register, sometimes the source value is old one that has not been updated by the RV32F instruction. 
 WHY : Incorrect instruction stallings. 
 FIX : Make the RV32F instruction in which its destination is XRn be multicycle instruction in each. Updated cpu_pipeline.v and cpu_fpu32.v.

### 2022.03.20 (2) Added Simple I2C and SDRAM Interface in FPGA
 Followings are updated. 
 (1) common/defines.v is divided into defines_core.v for mmRISC Core and defines_chip.v for Chip System. (defines.v is not used any more.) 
 (2) Simple I2C Core is added in FPGA. Related modifications are applied in RTL and Verification resources. Simple CPU Sample Program supports I2C which comunicates with Accelerometer Sensor on MAX10-Lite board. 
 (3) Simple SDRAM Interface logic is added in FPGA which accesses 64MB SDRAM on MAX10-Lite board. 
 0x80000000-( 64GB) SDRAM 
 0x88000000-( 48KB) Internal Data RAM 
 0x90000000-(128KB) Internal Instruction RAM 
 * The Technical Reference Manual has not been updated along with above updates. Please wait for a while.

### 2022.03.20 Fixed following bugs in Floating Point Instructions in mmRISC Core
 BUG1: FMV W.X and FMV X.W sometimes could not transfer correct data according to pipeline stall or wait-cycle timing. 
 WHY1: EX_FPU_DSTDATA was active only when EX_ALU_DST1 was asserted. 
 FIX1: EX_FPU_DSTDATA is connected from ex_busZ directly in cpu_datapath.v. EX_FPU_SRCDATA is stretched until next updating in cpu_fpu32.v. 
 
 BUG2: In FLW (load) followed by FMADD.S/FMSUB.S/FNMSUB.S/FNMADD.S, FMADDs did not use latest loaded data in src3. 
 WHY2: The register contention check between FLW's destination and FMADD's source 3 (src3) was not implemented. 
 FIX2: Contention check between FLW's destination and FMADD's source 3 (src3) is implemented in cpu_pipeline.v.

### 2022.02.12 Fixed a bug in HALT/RESUME operations of mmRISC Core
 BUG: Sometimes ignored HALT/RESUME Requests from Debugger during ID Stage is being stalled due to memory wait cycles. 
 WHY: DBG_HALT_ACK and DBG_RESUME_ACK are asserted in one cycle even during ID stallings. If these ACK signals are asserted, corresponding DBG_HALT_REQ and DBG_RESUME_REQ are immediately negated, then the pipeline control may ignore DBG_HALT_REQ and DBG_RESUME_REQ. 
 FIX: DBG_HALT_ACK and DBG_RESUME_ACK are asserted only at last of ID stages after its stalls in cpu_pipeline.v. 
 
### 2021.12.31 Some modifications except for mmRISC Core
Followings are updated. Main RTL Body of mmRISC is not modified due to no bugs found yet. 
 (1) Added MRET and WFI descriptions in Technical Reference Manual Rev.02. 
 (2) Supported Questa as logic simulator. To do so, add an option -voptargs="+acc" in vsim command. 
 (3) Supported Initialization of Instruction RAM in FPGA using .mif file. A conversion tool hex2mif is added in tools directory. 
 (4) Updated JTAG interface schematic. 
 (5) Changed operation of application mmRISC_SampleCPU. 
 (6) Add a retro text video game StarTrek as an application.

### 2021.12.26 Notes on Questa Sim
If you use Questa Sim to simulate mmRISC-1, please add an option -voptargs="+acc" in vsim command.

## ISA
RV32IM[A][F]C (configurable)

## Harts
Multi Harts Supported, 1 to 2^20 (configurable)

## Pipeline
For Integer : 3 to 5 stages 
For Floating Point : 3 to 6 stages

## Execution Cycles
Integer Multiplication MUL/MULH/MULHSU/MULHU : 1 cycle
Integer Division DIV/DIVU/REM/REMU : 33 cyles (Non-Restoring Method)
Floating Operations 
 FADD.S/FSUB.S/FMUL.S/FMADD.S/FMSUB.S/FNMADD.S/FNMSUB.S : 1 cycle 
 FDIV.S : 11 cycles (Goldschmidt's Algorithm) 
 FSQRT.S : 19 cycles (Goldschmidt's Algorithm) 
 The convergence loop counts for FDIV.S and FSQRT.S can be configured by software.

## Debug Support
External Debug Support Ver.0.13.2 with JTAG Interface 
Run / Stop / Step <br)
Abstract Command to access Register and Memory 
System Bus Access for Memory 
Hardware Break Points (Instruction / Data) x 4 (Configurable) 
Instruction Count Break Point x 1

## Privileged Mode
Machine-Mode (M-Mode) only

## Interrupt
IRQ_EXT : External Interrupt 
IRQ_MSOFT : Machine Software Interrupt 
IRQ_MTIME : Machine Timer Interrupt 
IRQ[63:0] : User IRQ, 64 inputs / Vectored Supported / 16 priority levels for each

## Counters
64bits MCYCLE (Clock Cycle Counter) 
64bits MINSTRET (Instruction Retired Counter) 
64bits MTIME (Memory Mapped Interrupt Timer)

## Bus Interface (AHB-Lite)
Instruction Fetch Bus 
Data Bus multiplexed with Debugger Abstract Command 
LR/SC Monitor Bus 
Debugger System Bus

## RTL
Verilog-2001 / System Verilog

## Verification
Vector Simluation 
RISC-V Compliance Test “riscv-arch-test” for I/C/M/Zifence/Privileged 
RISC-V Unit Test “riscv-tests” including Atomic and Floating Point ISA 
Comparison between TestFloat and RV32F on FPGA

## FPGA Proven
DE10-Lite Board (Intel MAX 10 10M50DAF484C7G) 
cTAG/JTAG Interface (FT2232D) 
Eclipse + Gnu Toolchains + OpenOCD

## Sample Programs
Simple CPU Sample Program 
Simple FPU Sample Program 
FreeRTOS Porting (Blinky) 
Dhrystone Benchmark 
Coremark Benchmark 
Retro StarTrek Game 
Touch LCD Panel Demo : Paint and Gravity Ball 
Touch LCD Panel Demo : Human vs CPU Tic-Tac-Toe

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