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fm-transmitter

★ 18 Open GitHub ↗

FPGA-based Fully Digital FM Transmitter using SDR (Software-Defined Radio) techniquies as up-converter using hpsdm, comb filters, cordic and so forth.

// repository documentation

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# FM Transmitter

This is an FM transmitter using just an FPGA. This project uses SDR
(Signal-Defined Radio) techniques to transmit an FM signal around 100MHz
frequency band using just the FPGA, without any other device.

- The current code transmits the microphone input in an FM signal at 99MHz.

For that, we are using the Techs:

- [CORDIC](src/sdr-tools/cordic.v) (COordinate Rotation DIgital Computer) algorithm
- [CIC](src/sdr-tools/cic_interpolator.v) (Cascade Interpolation Comb) filter
- Sigma-Delta Modulators (currently just high-pass).

Thus, we already built some blocks to implement our FM transmitter:

- [FM Modulator](src/sdr-tools/fm_modulator.v), essential block to
  modulate the input signal and put it into an intermediate frequency.
- [DUC](src/sdr-tools/fm_modulator.v) (Digital Up-Converter), block to
  send the intermediate signal to higher frequencies.
- [HPDSM](src/delta-sigma/hpdsm.v) (High-Pass Delta-Sigma Modulator)
  DAC. With such, we are able to send high frequency signals through a
  1-bit digital output, critical to our needs.

- **Current Documentations**:
  - [CORDIC](docs/cordic.md)

- Instructions to setup this project on your device are coming!

## Block Diagram

![Project Block Diagram](https://raw.githubusercontent.com/natanvotre/fm-transmitter/master/docs/images/project_diagram.png)

# Milestones

- [x] Blink led to test the Neek10 board
- [x] Add CI
- [x] Audio Loopback using data with sample rate of 48kHz
- [x] Create test environment and add on CI
- [x] Create and test sample interpolators to increase fs throughout the DUC (digital up-converter) chain, search for Comb filters
- [x] Create and test the frequency shifter to the DUC chain (search for
  CORDIC).
  - [x] Implement and test a CORDIC algorithm
  - [x] Make sure it is possible to shift in frequency complex signals
- [x] Create and test an HPSDM (High-Pass Delta-Sigma Modulator)
- [x] Create and test an FM modulator in medium fs
- [x] Create and test a DUC chain using the developed modules
- [x] Test high-frequency sinusoid output on-board
- [x] Test FM modulation and transmission with no input on-board
- [x] test FM transmitter using sinusoidal input
- [x] Test the FM transmitter on-board with audio input.
- [ ] (Optional) Replace AD from Codec by LPDSM (Low-pass Delta-Sigma Modulator)

# Features

- [x] Lint CI for Verilog
- [x] Makefile with
  - [x] Lint
  - [x] Test using [Pytest](https://docs.pytest.org/en/stable/) +
    [Cocotb](https://github.com/cocotb/cocotb) (also,
    [Cocotb-test](https://github.com/themperek/cocotb-test))
  - [x] Compile code using quartus platform
  - [x] Find and Program the Neek10 board, if attached on the computer
- [x] Loopback using (Board sanity-check):
  - [x] Onboarded Mic, which uses the ADC port for Max10 ADC protocol
  - [x] Line out of Onboarded CODEC IC [TLV320AIC3254](https://www.ti.com/lit/ds/symlink/tlv320aic3254.pdf?ts=1608386796342)
  - [x] Sample rate 48kHz
  - [x] Led meter to inform the audio energy
- [x] Sdr Tools
  - [x] Cic interpolator
  - Up-converter
    - [x] CORDIC algorithm
    - [x] Complete DUC.
  - [x] FM modulator
- [x] DA $\Sigma\Delta$ modulator
- [ ] AD $\Sigma\Delta$ modulator
- [x] FM transmitter
- [ ] Use an LPSDM (Low-Pass Sigma-Delta Modulator) instead of using the built-in ADC from Max10.

# CI

- Verilog lint;
- HDL unit tests using Cocotb + Pytest.
## Unit testing

For the tests, it has been used python, using Cocotb + Pytest to perform
the test benches.

It allows:

- Perform multiple types of tests using the same device
- Perform parametrized tests
- Test multiple devices separated
- Make assertions throughout the tests
- Save result files (as FFT, raw signal, etc)

Currently, there are tests for:

- [x] [reset_delay](src/utils/reset_delay.v) ([test file](tests/test_reset_delay.py))
  - Test if the parameter delay applies the correct delay
  - Assert if it is working
- [x] [sign_extend](src/utils/sign_extend.v) ([test file](tests/test_sign_extend.py))
  - Assert if it extends the signal of a set of values
  - Includes generated random values
- [x] [cic_interpolator](src/sdr-tools/cic_interpolator.v) ([test file](tests/test_cic_interpolator.py))
  - Test a set of sinusoids as input within different values of `WIDTH`
    and data length
      - Assert if the output sinusoids are correctly interpolated
      - Assert the output signal frequency
      - Assert the SNR for signals below $\frac{3}{4}\cdot \frac{fs}{2}$
      are greater than 30dB
      - Save input and output results, including the FFTs
  - Test the impulsive response of the Cic implemented
    - Using 32-bit WIDTH
    - Save impulse response output, raw and FFT
  - FFT setup using _hanning_ window to smooth side-lobes
- [x] [cordic](src/sdr-tools/cordic.v) ([test file](tests/test_cordic.py))
  - Test random complex input values (100 for each testcase) with random
    values and angles, including random rotational angles.
      - Assert whether the pipeline has the actual depth
      - Assert the circular rotation mode is working with the expected
        values, checking if the data was precise, error value less than
        5.
      - Assert the circular vectoring mode is working with the same
        approach.
- [x] [hpdsm](src/delta-sigma/hpdsm.v) ([test file](tests/test_hpdsm.py))
  - Test input sinusoids with different widths and frequencies
    - Assert whether the output contains the sinusoid
    - Check if around the pass-band the noise is low
- [x] [fm modulator](src/sdr-tools/fm_modulator.v) ([test file](tests/test_fm_modulator.py))
  - Test input sinusoids with different widths and frequencies
  - Test different intermediate frequency and output sample rates
  - Test different Fm sensibility constant (K)
  - Demodulate the signal, decimate, and check the SNR output signal.
- [x] [digital up-converter](src/sdr-tools/duc.v) ([test file](tests/test_duc.py))
  - Test input sinusoids with different widths and frequencies
  - Test different intermediate frequency and output sample rates
  - Test with Fs out = Fclk
  - Check the SNR of the output signal.
- [x] [transmitter](src/sdr-tools/transmitter.v) ([test file](tests/test_transmitter.py))
  - Just test signal integrity in the output
  - TODO: test different input signals.

fm-transmitter

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