Latency-Benchmarking-for-HFT-Simulator

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# Software Order Book Latency Benchmark

A synthetic high-frequency trading (HFT) style order book simulator for measuring **tick-to-trade latency** in software. This project does **not** connect to real exchanges; it generates deterministic market data locally and benchmarks multiple order-book implementations in Python and C++.

**Published benchmark numbers:** see [RESULTS.md](RESULTS.md) (100k packets, worst-case market model + lab comparison).

---

## What this project measures

| Benchmark layer | What is timed | Use case |
|-----------------|---------------|----------|
| **Core (V1–V3)** | `process_message()` + optional `get_top5_snapshot()` | Compare order-book data structures only |
| **Full pipeline (fast/lab)** | Packet decode → orderbook → snapshot → trading → encode | Compare engines on in-memory packets (no NIC/FPGA model) |
| **Realistic / worst-case** | Same pipeline + simulated NIC, ingress, FPGA-miss, risk, TX stalls | FYP / production-style tick-to-trade upper bound |

---

## Version evolution (workflow)

Each version keeps the **same market logic** (ORDER / CANCEL / TRADE, top-5 snapshot, trading rules). Only the **data structures and benchmark scope** change.

```mermaid
flowchart TB
    subgraph v1 [V1 — Python baseline]
        A1[dict OPB + dict FLB]
        A2[Snapshot = sort full book]
    end
    subgraph v2 [V2 — Python top-5 cache]
        B1[dict OPB + dict FLB]
        B2[Maintained top-5 cache]
    end
    subgraph v3 [V3 — Python direct array]
        C1[list OPB + price arrays]
        C2A[V3A: scan for snapshot]
        C2B[V3B: scan + top-5 cache]
    end
    subgraph v4 [V4 — C++ map baseline]
        D1[unordered_map OPB]
        D2[std::map FLB]
    end
    subgraph pipe [Full pipeline — all engines]
        E1[94 B packet in]
        E2[decode → OB → trade → encode]
        E3[~154 B packet out]
    end
    subgraph real [Worst-case market model]
        F1[NIC + userspace + SW decode stalls]
        F2[FPGA PCIe penalty + CPU OB/snap stalls]
        F3[Risk + TX queue stalls]
    end
    v1 --> v2
    v2 --> v3
    v3 --> v4
    v4 --> pipe
    pipe --> real
```

### How versions differ from each other

| Version | Language | OPB (orders) | FLB (price levels) | Snapshot strategy | Main trade-off |
|---------|----------|--------------|--------------------|-------------------|----------------|
| **V1** | Python | `dict` | `dict` bid/ask | Sort entire book every snapshot | Correct baseline; slow snapshots |
| **V2** | Python | `dict` | `dict` | Incremental **top-5 cache** | Fast snapshots; small cache maintenance cost |
| **V3A** | Python | `list` (direct index) | Price **arrays** | Scan price range for top-5 | FPGA-like addressing; **slow** snapshot scan |
| **V3B** | Python | `list` | Price arrays | Arrays + **top-5 cache** | Best Python balance in full pipeline |
| **V4** | C++ | `unordered_map` | `std::map` | Map iteration for top-5 | Same logic as V1; much faster in native code |

**Full pipeline** wraps any engine with `packet_codec` + `trading_logic` (spread / imbalance rules).

**Worst-case mode** wraps the full pipeline with `RealisticMarketPipelineEngine` — adds ~**26.8 µs** fixed simulated overhead per packet (feed handler, no FPGA offload, risk, TX). See [RESULTS.md](RESULTS.md).

---

## Requirements

- **Python 3.10+** (stdlib only for benchmarks)
- **CMake 3.12+** and a C++17 compiler (for V4 / pipeline binaries)

---

## Quick start

From project root (`orderbook_latency_benchmark/`):

```bash
# 1. Sanity check (V1 demo)
python3 -m python_impl.demo

# 2. Build C++
cmake -S cpp_impl -B cpp_impl/build -DCMAKE_BUILD_TYPE=Release
cmake --build cpp_impl/build

# 3. Final FYP report (worst-case tick-to-trade, all engines)
python3 -m python_impl.project_latency_report --n 100000 --mode worst_case
```

Outputs:

- `python_impl/results/tick_to_trade_latency_report.txt` — full text report
- [RESULTS.md](RESULTS.md) — committed summary for GitHub

---

## Project structure

```
orderbook_latency_benchmark/
├── README.md                     # This file — versions & workflow
├── RESULTS.md                    # Benchmark results (committed)
├── python_impl/
│   ├── orderbook_baseline.py     # V1
│   ├── orderbook_top5_cache.py   # V2
│   ├── orderbook_direct_array.py # V3A / V3B
│   ├── packet_codec.py           # Ethernet-like frames
│   ├── trading_logic.py
│   ├── full_pipeline.py          # Fast lab pipeline
│   ├── realistic_pipeline.py     # + market latency stalls
│   ├── market_latency_model.py   # Stall profiles (none / typical / worst_case)
│   ├── project_latency_report.py # One-shot FYP report
│   ├── benchmark.py              # Core benchmark (any engine)
│   ├── benchmark_v2.py / benchmark_v3.py
│   ├── benchmark_full_pipeline.py
│   ├── benchmark_realistic_pipeline.py
│   └── results/                  # Generated CSV/txt (gitignored)
├── cpp_impl/
│   ├── orderbook_cpp_benchmark              # V4 core
│   ├── orderbook_cpp_pipeline_benchmark       # Full pipeline (fast)
│   └── orderbook_cpp_pipeline_realistic       # Full pipeline (worst_case)
└── data/                         # Generated datasets (gitignored)
```

---

## Benchmark commands by version

### V1 — Python baseline (core only)

```bash
python3 -m python_impl.demo
python3 -m python_impl.benchmark --n 100000
```

Measures: per-message `process_message()` latency; periodic full-book snapshot sort.

### V2 — Top-5 cache (core)

```bash
python3 -m python_impl.correctness_compare
python3 -m python_impl.benchmark_v2 --n 100000
```

Compares V1 vs V2; expect large snapshot latency improvement for V2.

### V3 — Direct array engines (core)

```bash
python3 -m python_impl.correctness_compare_v3
python3 -m python_impl.benchmark_v3 --n 100000
```

Compares all four Python engines (V1, V2, V3A, V3B).

### V4 — C++ map baseline (core)

```bash
python3 -m python_impl.export_cpp_dataset --n 300000 --seed 42 --snapshot-every 1000
./cpp_impl/build/orderbook_cpp_benchmark \
  data/messages_300000.csv \
  data/expected_snapshots_300000.csv
```

### Full pipeline — lab / fast (no market stalls)

```bash
python3 -m python_impl.benchmark_full_pipeline --n 100000 --seed 42

python3 -m python_impl.export_packet_dataset --n 100000 --seed 42

./cpp_impl/build/orderbook_cpp_pipeline_benchmark \
  data/market_packets_100000.bin \
  data/expected_pipeline_100000.csv

python3 -m python_impl.project_latency_report --n 100000 --mode fast
```

### Full pipeline — worst-case (final FYP numbers)

```bash
python3 -m python_impl.benchmark_realistic_pipeline --n 100000 --profile worst_case

./cpp_impl/build/orderbook_cpp_pipeline_realistic \
  --profile=worst_case \
  data/market_packets_100000.bin

python3 -m python_impl.project_latency_report --n 100000 --mode worst_case
```

Optional moderate profile:

```bash
python3 -m python_impl.project_latency_report --n 100000 --mode typical
```

---

## Packet format (full pipeline)

- **Incoming:** 94 bytes — Ethernet (14) + IPv4 (20) + UDP (8) + payload (52), magic `0x4F424D44`
- **Outgoing:** ~154 bytes — magic `0x4F42534E`, trading decision, top-5 book, FNV-1a checksum

All engines must produce identical outgoing checksums on the same packet stream (verified in benchmarks).

---

## Simulated market delays (worst_case profile)

Configured in `python_impl/market_latency_model.py` (mirrored in C++ `MarketLatency.hpp`):

| Component | Worst-case (ns) | Meaning |
|-----------|-----------------|---------|
| NIC feed buffer | 1,500 | Packet waiting at feed handler |
| Kernel → userspace | 2,500 | Ingress copy / ring dequeue |
| Software decode stall | 3,500 | No hardware parser |
| FPGA missed (PCIe) | 4,000 | Book/snapshot not on FPGA |
| CPU orderbook stalls | 4,500 | Pre/post OB on CPU |
| CPU snapshot stalls | 4,000 | Pre/post snapshot on CPU |
| Trading + risk | 3,100 | Strategy + risk check |
| Encode + TX queue | 3,700 | Outbound framing + NIC queue |
| **Total fixed** | **26,800** | Added every packet before engine variance |

These are **deterministic busy-wait delays**, not measurements from real hardware. They model a CPU-only path when FPGA offload is unavailable.

---

## Price representation

Prices are **integers** (e.g. `10050` = 100.50) to avoid floating-point error. Default synthetic range: 9000–11000.

---

## Interpreting results

- Use **`--mode fast`** to compare order-book implementations with minimal external overhead.
- Use **`--mode worst_case`** for tick-to-trade numbers that include feed-handler and FPGA-bypass penalties.
- Prefer **p99** and **avg** over single **max** spikes (OS scheduling, rare Python pauses).
- **V3A** is expected to be slow on snapshot (full price-array scan); **V2 / V3B** are usually best in Python.
- **C++ V4** is fastest in lab mode; worst-case mode narrows the gap because everyone pays ~26.8 µs stalls.

---

## Planned extensions

- C++ direct-array + top-5 cache (V3-style in native code)
- Optional typical vs worst_case profiles in published tables
- FPGA-in-the-loop (real card) — out of scope for this software simulator

---

## License / academic use

Synthetic benchmark for coursework and research. Not suitable for production trading without full validation on real market infrastructure.

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