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# Open-Everything FPGA in Skywater130 (672x LUTs, 7x DSPs, 7x BRAMs)

[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0) [![UPRJ_CI](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/user_project_ci.yml) [![Caravel Build](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml/badge.svg)](https://github.com/efabless/caravel_project_example/actions/workflows/caravel_build.yml)

Demonstration of the fully open FABulous eFPGA using the OpenLane flow.

This repo experiments an implementation of an eFPGA from RTL to GDS with the open Skywater-130 PDK. The design RTL was generated by [FABulous framework](https://github.com/FPGA-Research-Manchester/FABulous). The fabric consists of 672x LUT4s (14x6 CLBs), 56x LUT5s (14x1 RegFiles), 7x DSPs and 7x BRAMs (7x1KB) with dual-ported memory blocks for register files and FIFOs. This version supports configuration over an embedded UART, a custom bitbang protocol and the wishbone bus.

The individual macros and the fabric were fully implemented using the [OpenLane flow](https://github.com/The-OpenROAD-Project/OpenLane.git) and integrated into [efabless caravel_user_project](https://github.com/efabless/caravel_user_project.git) wrapper.

## Project structure

The most important directories are described below:

* [dependencies](dependencies): Dependencies like the PDK.
* [doc](docs): Documentation, not changed compared to the template.
* [gds](gds): `gds` files of the macros and the top level design. 
* [lef](lef): `lef` file of the top level design.  Describes the physical layout
  in ASCII format.
* [lib](lib): `lib` file of the top level design. Describes the timing
characteristics of the design.
* [lvs](lvs): The config for the LVS of the top level design.
* [mag](mag): `mag` file of the top level design. Output of magic.
* [maglef](maglef): `maglef` file of the top level design. Output of magic.
* [openlane](openlane): The configuration and source files of all macros and the
  top level design.
* [scripts](scripts): Python and Bash scripts that helped during the design
process.
* [sdc](sdc): Constraints file for the top level design. Created by the
`write_sdc` command.
* [verilog](verilog): The Verilog source files used in the design.

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