MIPS-Processor

(β˜… 146)

5-stage pipelined 32-bit MIPS microprocessor in Verilog

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Download Latest Version (.zip)
  • Adder.v
  • ALU.v
  • ALUController.v
  • DataForwardingUnit.v
  • DataMemory32.v
  • Decoder.v
  • DFF.v
  • EX_MEM.v
  • Gates.v
  • HazardDetectionUnit.v
  • ID_EX.v
  • IF_ID.v
  • InstructionMemory32.v
  • JumpConcat.v
  • LeftShift.v
  • LICENSE
  • MainController.v
  • MEM_WB.v
  • Mux.v
  • Mux32.v
  • Mux5bit2to1.v
  • Pipelined Datapath.pdf
  • ProgramCounter.v
  • README.md
  • Reg32.v
  • RegFile.v
  • RegFile32.v
  • SignExtend.v

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