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FPGA-Agent
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FPGA-Agent
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> **My Claude account got banned.** ๐ If you find this project useful, consider sponsoring me to get a GPT Pro 20ร subscription โ I'd love to keep building. --- **This repo includes two parts:** 1. **Basic Skills** โ 8 FPGA/Vitis HLS development skills (below) 2. **Agentic-DSE** โ multi-agent FPGA HLS design space exploration system (at the bottom) --- # Vivado/Vitis FPGA Development Skills 8 skills covering AMD Vivado/Vitis 2025.2 FPGA development (RTL โ Bitstream + HLS), based on official UG documentation. ## FPGA Development Flow ``` HLS C/C++ โโโ RTL Design โโโ Synthesis โโโ Constraints โโโ Implementation โโโ Timing Analysis โโโ Programming/Debug vitis-hls synth constraints impl analysis debug Simulation (throughout): sim TCL Automation (throughout): tcl ``` ## Skills Overview | Skill | Documentation | Focus | Core Content | |-------|--------------|-------|--------------| | **vitis-hls-synthesis** | UG1399 | HLS Synthesis | Pragma optimization, interface config, dataflow/pipeline, burst optimization, synthesis report analysis | | **vivado-synth** | UG901 | Synthesis | Strategy selection, attributes (RAM_STYLE/USE_DSP/SHREG), resource inference, FSM encoding, OOC/incremental synthesis | | **vivado-constraints** | UG903 | Constraints | Clock definition, I/O delay, timing exceptions (false_path/multicycle), CDC, physical constraints, XDC debugging | | **vivado-impl** | UG904 | Implementation | opt/place/phys_opt/route directives, congestion analysis, incremental implementation, ECO flow, run strategies | | **vivado-analysis** | UG906 | Report Analysis | report_timing interpretation, slack calculation, QoR scoring (1-5), QoR suggestions, timing closure strategies | | **vivado-debug** | UG908 | Debug Strategy | ILA/VIO/JTAG-to-AXI selection, mark_debug flow, ILA config, Versal debug architecture, hardware programming | | **vivado-sim** | UG900 | Simulation | Behavioral/post-synth/post-impl simulation, xsim flow, third-party simulator integration, SAIF/VCD power simulation | | **vivado-tcl** | UG835+UG892 | TCL Execution | Project/Non-Project mode, command reference, IP Integrator BD, debug core insertion, hardware programming | ## Architecture Each skill uses a three-layer structure: ``` SKILL.md โ Decision guide (when to use what, strategy tables, decision trees) REFERENCE.md โ Command syntax (complete parameters, attribute tables, value ranges) examples/ โ Code examples (loaded on demand) ``` - **SKILL.md** auto-loads on skill trigger, focuses on decision knowledge - **REFERENCE.md** auto-loads on skill trigger, provides precise syntax - **examples/** not auto-loaded, read via index as needed ## Cross-References Between Skills ``` vitis-hls-synthesis โโโ vivado-impl (implementation), vivado-analysis (timing), vivado-constraints (top-level) โโโ vivado-sim (RTL simulation), vivado-debug (hardware debug), vivado-tcl (automation) vivado-synth โโโ vivado-tcl (execution) vivado-constraints โโโ vivado-tcl (execution), vivado-analysis (report interpretation) vivado-impl โโโ vivado-tcl (execution), vivado-synth (synthesis), vivado-constraints (constraints), vivado-analysis (analysis) โโโ vitis-hls-synthesis (HLS-level optimization) vivado-analysis โโโ vivado-tcl (execution), vivado-constraints (constraint modification), vivado-impl (strategy adjustment) vivado-debug โโโ vivado-tcl (execution), vivado-impl (strategy), vivado-analysis (timing) โโโ vitis-hls-synthesis (HLS debug options) vivado-sim โโโ vivado-tcl (execution), vitis-hls-synthesis (co-simulation) vivado-tcl โโโ vivado-debug (debug decisions), vivado-analysis (analysis), vitis-hls-synthesis (IP integration) ``` ## Examples Directory | Skill | Directory | Content | |-------|-----------|---------| | vivado-synth | `examples/` | 64 Verilog/SV files โ UG901 HDL coding templates (RAM/DSP/ROM/SRL/FSM) | | vivado-impl | `examples/ug906/` | 3 sets of before/after RTL โ report_qor_suggestions optimization examples | | vitis-hls-synthesis | `examples/` | Design/Feature/Introductory tutorials โ Official AMD HLS reference implementations | ## Command Verification All TCL commands referenced in skills have been verified through Vivado 2025.2 (`-help` test) to ensure they exist and are usable. --- # Agentic-DSE โ Multi-Agent HLS Design Space Exploration An agentic FPGA HLS design space exploration system. A Main Agent (architect + evolution scheduler) coordinates 3 Worker Agents to explore the Pareto-optimal frontier of FPGA designs through iterative refinement. ## How It Works ``` Main Agent (agent.md) โโโ Explorer Worker โ large-step mutation, explores new architecture/parameter space โโโ Exploiter Worker โ small-step fine-tuning, incremental optimization โโโ Innovator Worker โ feature-level crossover, fuses two parent designs โ T1 (checklist) โ T2 (synthesis) โ T3 (co-simulation) โ T4 (implementation) โ Pareto front update โ Hypervolume check โ Self-evolving knowledge base ``` Each round: the Main Agent analyzes bottlenecks, assigns tasks to all 3 Workers in parallel, collects validated results, and updates the Pareto frontier. The process converges when Hypervolume improvement drops below a threshold. ## What's In This Repo | File | Purpose | |------|--------| | `agent.md` | Main Agent instructions โ full orchestration protocol (`init req` โ `run dse` โ convergence) | | `prompts/architect.md` | Hardware Architect Agent โ selects architectures, analyzes critical paths, guides DSE direction | | `prompts/explorer.md` | Explorer Worker โ large-step mutation, bold architectural changes | | `prompts/exploiter.md` | Exploiter Worker โ small-step parameter/microarchitecture fine-tuning | | `prompts/innovator.md` | Innovator Worker โ feature-level crossover of two parent designs | | `prompts/req_parser.md` | Requirement Parser Agent โ converts user requirements into structured DSE configuration | | `prompts/coding_style.md` | HLS C++ coding style guide based on AMD UG1399, with anti-patterns and templates | | `prompts/hardware_checklist.md` | Pre-synthesis hardware checklist (A1โF5) + co-simulation quick diagnostic | ## Quick Start 1. **Prepare your design** โ Create `designs/<name>/` with `spec.json`, `src/kernel.cpp`, and `tb/testbench.cpp` 2. **Initialize** โ Run `init req <name>` with your requirements 3. **Explore** โ Run `run dse <name> [N]` to execute N rounds of DSE iteration ## What's NOT Included (Must Be Created by You or the AI Agent) This repo contains only the **agent prompt configuration**. The following are intentionally excluded and must be created at runtime: | Component | Description | How to Get | |-----------|-------------|------------| | **HLS synthesis skill** | Vitis HLS tool knowledge (commands, pragma reference, report analysis) | Use the `vitis-hls-synthesis` skill from this repo, or create your own | | **Knowledge base** | `knowledge/core/` (architecture catalog, platform specs) and `knowledge/learned/` (success/failure cases) | Auto-generated by the Architect Agent at runtime using its own knowledge, or pre-populated manually | | **Hypervolume script** | `hypervolume.py` for Pareto frontier HV computation (pymoo-based) | Generate via AI or write your own; Mode A is optional โ Mode B (simplified) and Mode C (manual) work without it | | **Benchmarks** | Reference designs and test vectors | Provide your own `designs/<name>/` directory with kernel source and testbench | | **Runtime state** | `state/`, `results/`, `tmp/` directories | Auto-created by agents during execution | ## Agent Platform Compatibility The prompts are platform-agnostic. Use with any AI agent system that supports: - Reading files (`Read`) - Writing files (`Write`) - Spawning subagents (`sessions_spawn` or equivalent) - Shell execution (for HLS synthesis commands)
