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vcd-samples

★ 43 Open GitHub ↗

sample VCD files

// repository documentation

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## GitHub

`https://wavedrom.live/?github=<user>/<repo>/<brunch>/<filename>.vcd`

#### Icarus
* https://wavedrom.live/?github=dpretet/vcd/master/test1.vcd
* https://wavedrom.live/?github=ombhilare999/riscv-core/master/src/rv32_soc_TB.vcd
* https://wavedrom.live/?github=b06902044/computer_architecture/main/CPU.vcd
* https://wavedrom.live/?github=phoeniX-Digital-Design/phoeniX/refs/heads/main/phoeniX.vcd
* https://wavedrom.live/?github=wanderingnail/AXI_DMA/refs/heads/master/build/DMAC.vcd

#### Verilator
* https://wavedrom.live/?github=wavedrom/vcd-samples/trunk/swerv/swerv1.vcd
* https://wavedrom.live/?github=bigBrain1901/nPOWER-ISA-5-STAGE-PIPELINED-CPU/master/post_compile_files/vlt_dump.vcd

#### GHDL
* https://wavedrom.live/?github=AdoobII/idea_21s/main/vhdl/idea.vcd
* https://wavedrom.live/?github=charlycop/VLSI-1/master/EXEC/ALU/alu.vcd
* https://wavedrom.live/?github=gaoqqt2n/CPU/master/SuperPipelineCPU/vcdfile/pcpu.vcd

#### VCS
* https://wavedrom.live/?github=sathyapriyanka/APB_UVC_UVM/5401170f6c74453c83f24df06ce9228c198f6d20/Apb_slave_uvm_new.vcd
* https://wavedrom.live/?github=Akashay-Singla/RISC-V/main/Pipeline/datapath_log.vcd
* https://wavedrom.live/?github=Akashay-Singla/RISC-V/main/2_way_Superscalar/datapath_log.vcd
* https://wavedrom.live/?github=ameyjain/8-bit-Microprocessor/master/8-bit%20microprocessor/processor.vcd

#### QuestaSim
* https://wavedrom.live/?github=mr-gaurav/Sequence-Counter/main/test.vcd
* https://wavedrom.live/?github=SparshAgarwal/Computer-Architecture/master/hw3/hw3_1/dump.vcd

#### ModelSim
* https://wavedrom.live/?github=sh619/Songyu_Huang-Chisel/main/MU0_final_version/simulation/qsim/CPU_Design.msim.vcd

#### QUARTUS_VCD_EXPORT
* https://wavedrom.live/?github=PedroTLemos/ProjetoInfraHard/master/mipsHardware.vcd

#### SystemC
* https://wavedrom.live/?github=jroslindo/Mips-Systemc/main/REGISTRADORES_32_bits/wave_registradores.vcd
* https://wavedrom.live/?github=amrhas/PDRNoC/VCRouter/noctweak/Debug/wavform.vcd.vcd

#### Xcelium (xmsim)
* https://wavedrom.live/?github=hwiiiii/RISCV64-Simple-CPU/main/sim/cpu.vcd
* https://wavedrom.live/?github=avidan-efody/wave_rerunner/main/test/data/integrated.vcd ⛔

#### treadle
https://wavedrom.live/?github=chipsalliance/treadle/master/src/test/resources/GCD.vcd

#### Aldec
* https://wavedrom.live/?github=SVeilleux9/FPGA-GPIO-Extender/main/Firmware/aldec/SPI_Write/SPI_Write.vcd (tgcd: 31000)

#### Riviera-PRO
* https://wavedrom.live/?github=prathampathak/Tic-Tac-Tao/main/dump.vcd

#### MyHDL
* https://wavedrom.live/?github=aibtw/myHdl_Projects/main/SimpleMemory/Simple_Memory.vcd
* https://wavedrom.live/?github=Abhishek010397/Programming-RISC-V/master/top.vcd
* https://wavedrom.live/?github=DarthSkipper/myHDL_Sigmoid/master/out/testbench/sigmoid_tb.vcd ⛔

#### ncsim
https://wavedrom.live/?github=amiteee78/RTL_design/master/ffdiv_32bit/ffdiv_32bit_prop_binom/run_cad/ffdiv_32bit_tb.vcd

#### xilinx_isim
* https://wavedrom.live/?github=mukul54/qrs-peak-fpga/master/utkarsh/utkarsh.sim/sim_1/behav/xsim/test.vcd
* https://wavedrom.live/?github=DanieleParravicini/regex_coprocessor/master/scripts/sim/test2x2_regex22_string1.vcd
* https://wavedrom.live/?github=pabloec1729/Hashes-generator/master/RTL/velocidad/test.vcd

### Vivado
* https://wavedrom.live/?github=saharmalmir/Eth2Ser/master/UART2ETH.runs/impl_1/iladata.vcd
* https://wavedrom.live/?github=BradMcDanel/multiplication-free-dnn/master/verilog/iladata.vcd

### GTKWave Analyzer
* https://wavedrom.live/?github=Asfagus/Network-Switch/main/perm_current.vcd (Late start. t0 > 0)

### Gist

`https://wavedrom.live/?gist=<user>/<hash>/raw/<hash>/<filename>.vcd`

https://wavedrom.live/?gist=drom/3b5f2ba5e2f60a91f9a8e765727858fe/raw/f79178d9e573d0957c065880b942882710a1660d/test1.vcd (Icarus)

https://wavedrom.live/?gist=carlosedp/00380f29bbd7aadc3523ffd162230d0e/raw/d732be78edb558ba91df5b3b1475288279df96fd/Blinky.vcd (Treadle)

## Bitbucket

`https://wavedrom.live/?bitbucket=<user>/<repo>/raw/<hash>/<filename>.vcd`

https://wavedrom.live/?bitbucket=alex_drom/vcd-samples/raw/36cf049c82f70f82249682d20444903627b9536e/test1.vcd (Icarus)

## GitLab

:construction: Does not work Yet :construction:

`Cross-Origin Request Blocked`

`https://wavedrom.live/?gitlab=<user>/<repo>/<brunch>/<filename>.vcd`

https://wavedrom.live/?gitlab=drom/vcd-samples/raw/main/swerv/swerv1.vcd (Verilator)

### Snippets

https://gitlab.com/-/snippets/2162111/raw/main/test1.vcd

# WaveQL fetch support

Second query source is an url of signal list file.

`https://wavedrom.live/?<host>=<path>.vcd&<host>=<path>.waveql`

https://wavedrom.live/?github=wavedrom/vcd-samples/trunk/swerv/swerv1.vcd&gist=drom/a641b8321d3d4b6d07e1a3bde302bb34/raw/03833b83748dd1ae17f151c9808d82d37a089711/swerv_ifu_axi_2.waveql

https://wavedrom.live/?github=dpretet/vcd/master/test4.vcd&github=wavedrom/vcd-samples/trunk/wave1.waveql

https://wavedrom.live/?github=wavedrom/vcd-samples/trunk/swerv/swerv1.vcd&github=wavedrom/vcd-samples/trunk/swerv_ifu_axi_2.waveql

vcd-samples

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