RISC-V-Pipelined-Processor

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RISC-V-Pipelined-Processor

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A Verilog based 5-stage fully functional pipelined RISC-V Processor code.

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# RISC-V Pipelined Processor

This is a verilog code for a 5-stage pipelined RISC-V Processor with forwarding, stalling, and flushing functionality. Here is the circuit diagramme of the processor.

![image](https://user-images.githubusercontent.com/56905673/117547053-f932fe00-b046-11eb-91af-9291291d4f52.png)

This is the semester project for the course Computer Architecture at Habib University. The instruction memory module is preloaded with Bubble Sort, implemented in RISC-V Assembly Language.

## Getting Started

These instructions will get you a copy of the project up and running on your web browser using EDA Playground.

### Instructions

For simulation purposes, open a new playground and load the testbench.sv and design.sv files. In the tab for design.sv, add all other sv files in the repository. In the 'Tools and Simulator' tab, choose 'Mentor Questa 2020.1'. Do not specify a run time.

## License

This project is licensed under the MIT License - see the [LICENSE.md](LICENSE.md) file for details

## Acknowledgments

* Habib University for the course on Computer Architecture.
* Aiman Najeeb, the RA for this course, for the troubleshooting help, lab manuals, and step by step guidance in building this project.
* 2 group members, Lama Imam and Ayeza Nasir for building all the pipeline registers and Forwarding Unit.

RISC-V-Pipelined-Processor

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