awesome-eda

KO | EN

gitlite — search

#hacktoberfest #ai #typescript #llm #go #golang #android #machine-learning #rust #deep-learning #macos #java #kubernetes #awesome-list

(★ 103)

No description available.

awesome-eda Latest Version Download

Download Latest Version (.zip)

// repository documentation

Was this content helpful?

★ 0 (0 ratings)

# Awesome Open Source EDA Projects
> A curated list of EDA open source projects. 
Please feel free to update this page through [submitting pull requests][GitHub pull requests] or [emailing me][email me].

## Table of Contents
* [1999](#1999) 
* [2002](#2002) 
* [2004](#2004) 
* [2005](#2005) 
* [2009](#2009) 
* [2010](#2010) 
* [2011](#2011) 
* [2012](#2012) 
* [2013](#2013) 
* [2014](#2014) 
* [2015](#2015) 
* [2016](#2016) 
* [2017](#2017) 
* [2018](#2018) 
* [2019](#2019) 
* [Summary](#summary) 
* [Reference](#reference)

## Projects (sorted by year)

### 1999
* [ngspice](https://github.com/imr/ngspice)

### 2002
* [xyce](https://xyce.sandia.gov/)

### 2004
* [Hierarchical Asynchronous Circuit Kompiler Toolkit](https://github.com/fangism/hackt)

### 2005
* [Berkeley-abc](https://github.com/berkeley-abc/abc)

### 2009
* [CVC4](https://github.com/CVC4/CVC4)

### 2010
* [Galois Parallel Framework](https://github.com/IntelligentSoftwareSystems/Galois)

### 2011
* [Asynchronous Circuit Compiler](https://github.com/asyncvlsi/act)

### 2012
* [PyMTL: Python-based hardware modeling framework](https://github.com/cornell-brg/pymtl)
* [Yosys Open SYnthesis Suite](https://github.com/YosysHQ/yosys)
* [Verilog to Routing -- Open Source CAD Flow for FPGA Research](https://github.com/verilog-to-routing/vtr-verilog-to-routing)

### 2013
* [Qrouter](http://opencircuitdesign.com/qrouter/2013)

### 2014
* [Graywolf](https://github.com/rubund/graywolf2014)
* [Limbo](https://github.com/limbo018/Limbo)

### 2015
* [OpenTimer: A High-performance Timing Analysis Tool for VLSI Systems](https://github.com/OpenTimer/OpenTimer)
* [Ophidian: Open-Source Library for Physical Design Research and Teaching.](https://gitlab.com/eclufsc/ophidian)
* [OpenMPL](https://github.com/limbo018/OpenMPL)

### 2016
* [A Modeling and Verification Platform for SoCs using ILAs](https://github.com/Bo-Yuan-Huang/ILAng)
* [Mixed Hardware/Software Emulation](https://github.com/Xilinx/systemctlm-cosim-demo)
* [SystemC TLM Interfaces](https://github.com/Xilinx/libsystemctlm-soc)
* [BoxRouter (Global Router)](https://github.com/krzhu/BoxRouter)

### 2017
* [Rsync](https://github.com/RsynTeam/rsyn-x)
* [Cloud-V](https://github.com/Cloud-V)
* [HAMMER:Highly Agile Masks Made Effortlessly from RTL](https://github.com/ucb-bar/hammer)
* [Magic](https://github.com/libresilicon/magic-8.22017)
* [GDS Viewer](https://github.com/KLayout/klayout)

### 2018
* [Lgraph: Live Graph infrastructure for Synthesis and Simulation](https://github.com/masc-ucsc/lgraph)
* [OpenPiton](https://github.com/PrincetonUniversity/openpiton)
* [Cpp-Taskflow](https://github.com/cpp-taskflow/cpp-taskflow)
* [Parser-SPEF](https://github.com/OpenTimer/Parser-SPEF)
* [DATCRobustDesignFlow](https://github.com/jinwookjungs/datc_robust_design_flow)
* [EPFLLogicSynthesisLibraries](https://github.com/lsils/lstools-showcase?)
* [OpenSTA](https://github.com/abk-openroad/OpenSTA)
* [RePlace](https://github.com/abk-openroad/RePlAce)
* [TritoCTS](https://github.com/abk-openroad/TritonCTS)
* [TritonSizer](https://github.com/abk-openroad/TritonSizer)
* [BSD-DME](https://github.com/abk-openroad/BST-DME	)
* [LeWiz Communications Ethernet MAC Core2 10G/5G/2.5G/1G](https://github.com/lewiz-support/LMAC_CORE2)
* [LeWiz Communications, Inc. Ethernet MAC Core1 - Ethernet 1G/100M/10M](https://github.com/lewiz-support/LMAC_CORE1)
* [12nm RAIL library](https://github.com/rail-posh/rail12)
* [65nm RAIL Library](https://github.com/rail-posh/rail65)
* [A framework for FPGA emulation of mixed-signal systems](https://github.com/sgherbst/anasymod)
* [AXI Protocol Checker](https://github.com/upscale-project/case-studies/tree/master/axi)
* [CoreIR Symbolic Analyzer](https://github.com/cristian-mattarei/CoSA)
* [Open-source FPGA Workflow](https://github.com/PrincetonUniversity/prga)
* [FPGA-SPICE](https://github.com/LNIS-Projects/OpenFPGA)
* [Tools regarding on analog modeling, validation, and generation](https://github.com/StanfordVLSI/DaVE)
* [OpenDP (Open Source Detailed Placement)](https://github.com/sanggido/OpenDP)
* [University of Minnesota / Intel (Automated Analog Layout)](https://github.com/ALIGN-analoglayout/ALIGN-public)
* [gds2Para (Complete Integrated Circuit (IC) Layout Analysis from GDSII Design File to Parasitics Extraction)](https://github.com/purdue-onchip/gds2Para)
* [University of Utah (Logic Synthesis)](https://github.com/LNIS-Projects/LSOracle)
* [JITX (Intent Driven Board Design)](https://github.com/JITx-Inc/darpa-idea)
* [The EPFL Combinational Benchmark Suite](https://github.com/lsils/benchmarks)

### 2019
* [Analog Known Good Designs](https://github.com/USCPOSH/AMS_KGD)
* [Analog Parameter Search Engine](https://github.com/USCPOSH/AMPSE)
* [Brown (Open Source PVT Sensors)](https://github.com/scale-lab/PVTsensors)
* [Circuit IP Sanitizer](https://github.com/USCPOSH/Sanitizer)
* [Serial Link Mixed Signal Modeling](https://github.com/upscale-project/hslink_phy)
* [UW-IDEA_AnalogTestCases](https://github.com/uwidea/UW-IDEA_AnalogTestCases)
* [System Verilog to Verilog](https://github.com/umich-cadre/sv2v)
* [Asynchronous Memory Compiler](https://github.com/asyncvlsi/AMC)
* [University of Michigan (Intent Driven Analog Design)](https://github.com/idea-fasoc/datasheet-scrubber)
* [Machine Generated Analog IC Layout](https://github.com/magical-eda/MAGICAL)
* [Magical Test Circuits](https://github.com/magical-eda/MAGICAL-CIRCUITS)
* [UW BSG Pipecleaner Suite](https://github.com/bespoke-silicon-group/bsg_pipeclean_suite)
* [OpenPiton Design Benchmark](https://github.com/PrincetonUniversity/OPDB)
* [System Verilog to Verilog](https://github.com/bespoke-silicon-group/bsg_sv2v)
* [Utd-SystemVerilog](https://github.com/billswartz7/utd-SystemVerilog)

## Summary

| Year | Number | Cumulative Number |
| :--- |  :---:  | :---: |
| [1999](#1999) | 1  | 1 |    
| [2002](#2002) | 1  | 2 | 
| [2004](#2004) | 1  | 3 | 
| [2005](#2005) | 1  | 4 | 
| [2009](#2009) | 1  | 5 | 
| [2010](#2010) | 1  | 6 | 
| [2011](#2011) | 1  | 7 | 
| [2012](#2012) | 3  | 10 | 
| [2013](#2013) | 1  | 11 | 
| [2014](#2014) | 2  | 13 | 
| [2015](#2015) | 3  | 16 | 
| [2016](#2016) | 4  | 20 | 
| [2017](#2017) | 5  | 25 | 
| [2018](#2018) | 28  | 53 | 
| [2019](#2019) | 15  | 68 |

## Reference
* T.-W. Huang, C.-X. Lin, G. Guo, and Martin D. F. Wong, [Essential Building Blocks for Creating an Open-source EDA Project][DAC19 paper], ACM/IEEE Design Automation Conference (DAC), Las Vegas, NV, 2019.
* [Essential Building Blocks for Creating an Open-source EDA Project][DAC19 slides]. Invited talk at DAC.
* [DARPA Intelligent Design of Electronic Assets (IDEA)][DARPA IDEA] 
* [DARPA Posh Open Source Hardware (POSH)][DARPA POSH]
* [List of IDEA Projects][DARPA IDEA GitHub] 
* [List of POSH Projects][DARPA POSH GitHub]

* * *

[GitHub pull requests]:  https://github.com/clin99/awesome-eda/pulls
[email me]:              mailto:twh760812@gmail.com 
[DAC19 slides]:          https://tsung-wei-huang.github.io/talk/dac19-invited.pdf 
[DAC19 paper]:           https://tsung-wei-huang.github.io/papers/dac19-invited.pdf
[DARPA IDEA]:            https://www.darpa.mil/program/intelligent-design-of-electronic-assets  
[DARPA POSH]:            https://www.darpa.mil/program/posh-open-source-hardware
[DARPA IDEA GitHub]:     https://github.com/aolofsson/IDEA 
[DARPA POSH GitHub]:     https://github.com/aolofsson/POSH

awesome-eda

awesome-eda Latest Version Download

Today's picks

Was this content helpful?

Recent Feedback

awesome-eda

awesome-eda Latest Version Download

Today's picks

Was this content helpful?

Recent Feedback

Download README