lpddr4-test-board

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lpddr4-test-board

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Experimental development board interfacing Xilinx Kintex-7 FPGA with LPDDR4 SDRAM

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# LPDDR4 test board

[![LPDDR4 test board @ opensource.antmicro.com](https://img.shields.io/badge/View%20on-Antmicro%20Open%20Source%20Portal-332d37?style=flat-square)](https://opensource.antmicro.com/projects/lpddr4-test-board)

![LPDDR4 test board](https://raw.githubusercontent.com/antmicro/lpddr4-test-board/main/img/lpddr4-test-board.jpg)

## Overview

This repository contains open hardware design files for an experimental platform built around Xilinx Kintex-7 FPGA.
The main purpose of this platform is to develop and customize RAM controllers supporting LPDDR4 ICs.

This hardware platform is supported by the [Rowhammer Tester](https://github.com/antmicro/rowhammer-tester) gateware.
It can be used to investigate Rowhammer DRAM attacks.
You can learn more about Rowhammer attacks from this blog [note](https://antmicro.com/blog/2021/08/open-source-ddr-test-framework-for-rowhammer/).
The usage instructions for this board are also provided in the [Row Hammer Tester documentation](https://rowhammer-tester.readthedocs.io/en/latest/).

The design files for this board were prepared in KiCad 9.x.

## Repository structure

The main repository directory contains KiCad PCB project files, a LICENSE and README.
The remaining files are stored in the following directories:

* `img` - contains graphics for this README

## Key features

* Kintex-7 FPGA - XC7K70T-FBG484
* Modular design with custom DDR4 SO-DIMM connector for various testbeds
* HDMI output connector
* Ethernet RJ45 connector with 1GbE transceiver
* Micro USB debug connector with FT4232HQ FTDI USB controller
* JTAG
* microSD card slot
* 16Mbytes S25FL128S QSPI FLASH memory
* S27KL0641 HyperRAM
* External 7-12V power input
* 5 user LEDs
* 4 user buttons

The LPDDR4 test board is electrically compatible with the following testbeds:

* [LPDDR4 Testbed](https://github.com/antmicro/lpddr4-testbed) with a single LPDDR4 IC
* [DDR5 Testbed](https://github.com/antmicro/ddr5-testbed) with a signle DDR5 IC

## Block diagram

![Block diagram](https://raw.githubusercontent.com/antmicro/lpddr4-test-board/main/img/lpddr4-test-board-diagram.png)

## Licensing

This project is published under the [Apache-2.0](LICENSE) license.

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